Great, some 3D representations of the boards. If this is all they have at the moment, then I would say the shipments are a hell of a long way off. We now return to our originally scheduled program: http://www.youtube.com/watch?v=DIslhp9vqqw
awww
Topic: 25-09-2012: First Look at BFL's ASIC Hardware (Coding In My Sleep) (Read 1849 times)
September 29, 2012, 11:56:40 PM
awww
September 27, 2012, 11:26:24 AM
Great, some 3D representations of the boards. If this is all they have at the moment, then I would say the shipments are a hell of a long way off. We now return to our originally scheduled program: http://www.youtube.com/watch?v=DIslhp9vqqw
This image could be from 4 months ago.... they are not going to publicly release the most current info!
September 27, 2012, 10:51:50 AM
This shows a simple assumption of mine is probably right. I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips. Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40..... Maybe I am wrong or the Jalapeno is downclocked?
The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.
September 27, 2012, 08:47:07 AM
This shows a simple assumption of mine is probably right. I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips. Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40..... Maybe I am wrong or the Jalapeno is downclocked?
The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.
Is there going to be some fan with jalapeno?
September 26, 2012, 11:44:12 PM
This shows a simple assumption of mine is probably right. I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips. Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40..... Maybe I am wrong or the Jalapeno is downclocked?
The current theory is that the chips are made and the ones that don't rate 5.0 GHps get put into the Jalapeno pile.
September 26, 2012, 11:03:45 PM
This shows a simple assumption of mine is probably right. I thought that the Jalapeno would be a single chip and the single would not be a single but a combination of Jalapeno chips. Of course the math does not add up, I see 8 ASICS there and 8 x 3.5 does not equal 40..... Maybe I am wrong or the Jalapeno is downclocked?
September 26, 2012, 03:20:44 AM
Great, some 3D representations of the boards. If this is all they have at the moment, then I would say the shipments are a hell of a long way off. We now return to our originally scheduled program: http://www.youtube.com/watch?v=DIslhp9vqqw
September 26, 2012, 02:42:57 AM
Nice.
But it looks to me like this is not the final version of the board, because some components are hanging over the edge of the PCB.
September 26, 2012, 02:34:55 AM
Very neat.
September 26, 2012, 02:18:01 AM
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