The source for your "4x claim" is quoted below. I did not remember that you also said that 10x is at the far end of the possible. So, since 45nm FPGAs do 20 Mhash/J, should I interpret your claim as 200 Mhash/J barely doable with really good engineers on a 45nm ASIC? On top of that, most people (including me) don't believe BFL has the capital to develop at 45nm. 65nm would be more realistic, which would put them at half the efficiency, or 100 Mhash/J.
I still don't understand why you don't take the bet, since I place the bar much higher, at 350 Mhash/J.
In case my intentions aren't clear: I am pushing you to either (1) make you bet money (even a symbolic amount), or (2) force you to concede that 350 Mhash/J is plausible (which would be a reversal of your previous claims, see below)
Another thing that makes the BFL announcement rather
of hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.
I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.
I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).
of hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.
I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.
I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).
This.
Just taking your FPGA-tested verilog and pushing it through the Synposys tools will usually get you an ASIC with 4x power improvement.
Working really hard to re-do the design from scratch will get you 8x. Maybe 10x if you have really good engineers.
A 56x improvement in power consumption is just plain absurd.
