Topic: 55nm Bitfury chips - Direct 220V Project (Read 3834 times)

Nice!

Glad to see somebody is still doing it.

I have finally received the boards from the assembly house



Hope to test them (one by one at low voltages) this weekend and that there will be no bad chips. There are still some unpopulated chips left, but repairs are difficult

Right, I've got a whole box of 470uF 250V pulls from old supplies. I got a box of retired (working) Dell server supplies I could scrounge some 330uF 450V Nichicons out of if you're interested.

I see the point of reducing losses, but as noted earlier, the nonlinearity in your rectifier is gonna give you a pretty terrible power factor. Course, for just a test, that's probably not too bad. I'm looking forward to your results with an Active PFC load. I actually suggested something similar to a guy a couple years ago who was trying to figure out how to chain S5s onto a 277V line.

Yes, that was the initial idea, but I have checked few broken ATX supplies (350-450W nothing more powerful ) at hand and they are all with 370uF 250V capacitors, so will need even more of them.
Also there is a risk with used ones, because their state is unknown.

The inductors in the passive PFC will increase the losses in addition to reducing the ripple currents, while I want to reduce the losses at minimum.
The choice for 450V is to be able to test with active PFC later and the increased capacitance will reduce the voltage ripple there too even if unnecessary.

There is one more advantage with multiple 100uF capacitors actually - will be able to test the effect of different values (voltage ripple) on the hashrate and stability.

Ever think about just stealing the passive PFC rectifier/cap portion out of an old ATX supply? Seems like that's most of what you're trying to build anyway, and around a 400W supply should be input-rated for your draw.

Small update.

While waiting for the assembly house to populate the boards ( slow cheap order 2+ weeks to wait ) I have started with the power part and the sad thing is that, even we need just 330uF capacitor it can't survive the RMS currents, so instead of 2 or 3 220uF as planned will need to go with 5 to 10 100uF capacitors in parallel.
The inrush current will be limited with AMETHERM - SL22 40005 (probably 2 of them) or EPCOS - B59201J0140B010
Instead of choke and transil will use stock Surge Protector Power Strip which has them inside already and will also protect other equipment later.

Thank You, but I hope not to need more as unsoldering from old boards will be a nightmare.

That's my intention. As I said I have a working string on 24V DC (in fact 26V). The key here is the use of the CMQ - immediately after plugging it in the outlet the string self-tunes to ~1.5A. When latter the miner is started on the RPI, it configures the chips with 52 bits clock (~190MHz) during the detection phase, which is later increased to 54 bits (~215MHz) or 55 bits (~230MHz). This is enough as startup procedure at the moment and hopefully will be enough for a longer strings to. Just in case it's not, there is plan B - the miner (with my own changes and web interface) allows changing the bits for each/any chip at runtime, so a simple external/web script can do that very easy.

Bitfury stuff loves to run in strings. Remember they built 48V single-wide strings for their own DCs and apparently got along well enough.

Are you running this off a single phase 230v line? Id love to see this work, but hate to say that running a 300-400 line string would surely end in disaster. There is a reason why most ASIC boards have very short strings, and some multiple strings in parallel. Its hard enough to provide clean power to the asics with a clean 12v DC power input...trying to do that with an a single phase AC line on a 400 line string is insane lol. The ONLY way this would be possible is if you have some very sophisticated startup and hash phase loop control down to each asic (I guess this could be implemented fairly straighfoward by controlling the PLL clock for each chip seperatly, but that would still be a coding nightmare, and not sure what kind of device you would need to have to control 400 I/Os in sync   .

Hit me up if you ever need more chips. I have hundreds of the old bitfuy H cards

STEP 3 - Filtering capacitors
For a stable operation usually several mF capacitor would be required for such setup, but because of chip specifics we can go with much smaller capacitor (values in uF):

	205V AC	220V AC	230V AC	235V AC	265V AC
392 chips	152.37	101.94	85.18	79.1	57.65
406 chips	198.58	117.39	94.44	86.53	60.23
420 chips	295.24	140.56	107.19	96.47	63.43
434 chips	618.47	178.67	125.6	110.27	67.41
448 chips	X	252.12	154.17	130.45	72.42

And the same calculations with 2A current

	205V AC	220V AC	230V AC	235V AC	265V AC
392 chips	181.3	113.02	90.34	82.1	53.07
406 chips	244.72	134.8	103.74	93.02	57.42
420 chips	376.39	166.97	121.8	107.28	62.56
434 chips	814.74	219.32	147.47	126.72	68.7
448 chips	X	319.48	186.86	154.74	76.18

My expectation was for 600-700uF and as it turns out it's close enough for the worst case (434 chips @ 205V), but if we can accept miner resets when the voltage drops below 220V stock 330uF should suffice for 448 chips and we can even go with just 120uF for 392 chips
There is no way to run 448 chips at lowest voltage ( 205V ) except if we reduce the current below the optimal by setting clock bits below 50. For lower J/GH that's an option, but my broads are designed around the optimal power point (1.8A @ 0.8V) and even that will not help, because the CMQ will try to bring them there (~1.5A actually).

Just to make it clear, because few people have PMed me with similar questions ...
This project will not bring back to live your old Bitfury gear nor it will make the 55nm chips profitable again.
The production cost is over 1BTC while 1TH miner with free electricity will make 0.05 say 0.1BTC for it's entire live.
I put money in this project for fun (as a hobby), not for profit!

I have enough chips for the initial tests, so there is no need of more (for now). For the PFC tests i may use some of my old (damaged) boards if nothing catastrophic happens with the rest of the boards.

Not 230V DC but 325V DC = SQRT(2) * 230V ~= 1.4 * 230V

I have some PCBs printed for the 55nm and got some chips for free. Just the assembly will cost ~0.5 BTC and will need some other parts too while this is a hobby project and can't afford to spend on recent chips.

With the 16nm chips it will be definitely possible too (if this one works), but it will be much more difficult - more stable voltage will be required (i.e. setup with PFC, because the CMQ was removed) there should be dedicated SPI/controller for each 50-100 chips, while the setup will take ~870 of them and ~110 of their levelshifters add to that ~20 controllers and you will get a 50-60TH monster eating ~4kWh, which a single 16A circuit won't handle

Interesting. Why not try with recent chips?

am i missing something - how are you turning your 230V AC into 230V DC for the chips?

Upon reflection, might try getting in touch with MegaBigPower and see if they still have their old 55nm Bitfury gear around and are willing to sell it.

Looking at this again ... the PFC might be really better for the efficiency and those 10W-20W wasted in the PFC will be compensated by not having the performance drop caused otherwise.

PFC will need 504 chips (next step 9 panels) and lower (~240kHz) max SPI, but as it turns out it should still be enough for proper communication.

I will be few chips short for 9 panels and there will be no chips left for replacements after the fireworks, but will definitely try the PFC setup if enough chips survive the first tests

STEP 2 - determine the number of chips limit for the string based on SPI speed

Each chip has 4ns propagation delay of the signal, which places limit on the number of chips one can access with a single SPI (in a single string)

For 448 chips the maximum SPI speed possible is ~279kHz - let's use 200kHz (may need to be lowered further down to 100kHz) for noise immunity.

Expected GH per chip (they are Rev2) is calculated as MHz * 0.864 / 65 and optimal 235MHz (1.8A @ 0.81V with 392 chips) = 3.1GH with total of 1.2TH @ ~600W
For 448 chips expecting 1.7A @ 0.74V and ~180MHz which is 2.4GH or total 1TH @ ~560W

Each communication is ~100 bytes, so 2000 at 200kHz and 1000 at 100kHz. In all cases we will have at least 2 communications per second per chip, which should be enough not to miss shares and to send the next job to the chip in time, as it will take ~1.1sec per job with 3.1GH.

The real speed will be lower (because of HW errors and speed drop with the voltage) and the power used a bit more (because of the required fan and the current limiter + some other components), but 0.6J/GH seems possible target at max possible clock bits for that voltage.
It may go further down with lower clocks with expected minimum of 0.45J/GH for ~500GH, which is impressive for such old chip, but TBD ...

Yep, that's what I was talking about. The 55nm chips have some very neat specs that allow running on mostly bare chips in long strings.

The negative temperature coefficient is accounted for in my design using another peculiarity of the chips - the built in current mirror (CMQ). As I said the voltage is almost perfectly (blaming component tolerances mostly) balanced and the CMQ response is few nanoseconds

Sad but true. My next post will be about that, but so far it's not looking too bad.
Will use RPI (initialy) mostly because I have a working miner with it and it will be easier to modify the code at runtime.
Level shifting is required only to the first chip 3V3 <-> 1V8 (actually ~1V6 = doubled core voltage). And (from my next post) the SPI speed should be so low that even a simple discreet elements LS should be fast enough, while SN74AVC4T774 will be used.

But in this case the load varies with the voltage too, so they balance each other for free.
One farad at 400V ?!? Don't want to sell a kidney, so no, but yes - the filtering capacitor will be the most demanding part (will post about that in STEP 3)

but now ...

The old 55nm chips were designed to string without an external level shifter. Maybe some passives between chips, but nothing serious. Take a look at the old OneString boards, they're pretty barebones.

Well, Bitfury (corporation) and Punin (person) promised to release the specifications for their communication controller/level shifter/differential transceiver chip.

Bitfury Designs released under CC-BY-SA

https://bitcointalksearch.org/topic/bitfury-designs-released-under-cc-by-sa-1360038

Maybe sidehack has some information in English now? I vaguely remember seeing some posts in Russian that are now deleted, and I'm only quarter-literate in Russian.

I think , that power part of the design is not going to be bottleneck , here.
The SPI will be pain in the ass, You will have to use some kind of level shifting.
RPI is too much of  a mess for my taste too

No coin miner is ever standard. The main fun is that they invalidate all standard design flows: they either lead to failure or vast over-specification and under-performance.
As far as I know several people tried to use the internal self-clocking and reported problems with them: not always starting reliably and humongous jitter. My experience (not with mining, but with somewhat similar digital-but-nearly-analog chips) is that you are better off forcing your own external clocking and very frequently run short test mining jobs with known answers (like once every second feed the chip a job that requires just a few increments to find the golden nonce).
This is where I disagree with you the most. The failure modes of MOS devices are really strange, silicon has negative temperature coefficient and is prone to creating hot spots, where the device fails way below their normal rated specifications when the dI/dt or dV/dt was too fast. Hopefully you'll get your 55nm Bitfurries really cheap so you won't regret skimping on the safeties. But speccing and acknowledging the need for parallel transil is a good start.

My school had a program sponsored by International Rectifier (www.irf.com), we could burn power semiconductors for free (provided that we documented the conditions of the burn) and I still have some fond memories from that time.

I've seen your "back of the envelope" calculations and basically I suggest that you get a bigger envelope and make some more calculations. In particular, don't always assume that Vpeak/Vrms = 1.4, it varies widely with the load.

Or maybe just want want to go for the shock value and use one farad capacitors in your ripple filter, the ones that are used by the bass-heavy car audio enthusiasts. 

2112, I am not a noob, but I am not a professional hardware developer either, so I may be missing some aspects, which will byte me in the butt latter ... but then I'll learn which is a win

It's neither 1 or 2, but for fun and will definitely learn something new while working on it ... well its close to 1, except it's not over-specification, but around chip specifics.

not a bet, but because no one thinks it's possible and because the chip has some specifics will allow to do that by working on the edge (and beyond)

One thing is for sure it's far from 2) there is no fun in standard designs (just copy paste and recalculate), but the chip is also not standard
There will be continued project latter to replace the RaspberryPI and existing software with ESP32 or ESP8266, but that's not for the hardware forum and as free time project will probably take several months.

See my previous post - the chip speed and consumption depends on the clock which is internally generated and voltage dependent, so we have this for free

For protection against spikes a choke and inrush current limiter before the capacitor should be enough: ~400 chips string may survive spikes up to 600V DC, but then the current is 3.5A, so if limited to 2A the transistor should take that load and just in case planning to add a 400V transil in addition.

RadekG

1. Yes, there are some advantages with PFC, but also more losses and then it is better to just use stock PSU for lower voltage being much safer too
2. The current limiter is for the extreme situations if something goes wrong, but the transistor will be fully open most of the time and the actual current will be controlled with chip's clock speed.
3. It will be filtered, but just enough that the voltage does not drop below 0.65V per chip at say 2A, so much lower capacitor than a dozen of mF will be needed. Also the chip speed and power consumption depends on the voltage and will go down with the voltage, so much less than 2A at lower voltages and much smaller capacitor for the trade of some speed. If there are more chips then the current will also be much less than 2A initially even if lower voltage drop is allowed.
4. see 2. the transistor will dissipate say 2A at ~0.6V-1V and before the capacitor there will be just inrush current limiter

Yeah, it will most certainly work, when designed correctly. I'm still perplexed why you were concerned about few percentage point of RMS voltage variation (220-235V or 205-265V) while your main concerns should be ripple and protection against spikes.

Ripple itself on a single-phase system would be around 40% (25%-50% if I remember correctly) unless you drastically over-design the ripple filter and your rectifier diodes conduct only during few percents of the mains cycle. I'm unclear what is the purpose of your design: (1) show that it is possible using ridiculous over-specification or (2) an experiment in a proper power electronics design that could be practically scaled up and deployed later.

In case (1) you just don't worry about inductive spikes in the mains voltage because you ridiculously over-specified capacitors.

In case (2) you have to have proper protection against spikes. I don't have specific information about Bitfury's chips, but in metal-insulator-semiconductor chips the over-current protection is typically not enough. The breakdown is not only thermal, it involves electromigration of metal over insulator and insulator under metal. Electromigration is both irreversible and cumulative. In normal industrial practice you will need parallel over-voltage shunt to extinguish the inductive spikes coming from the mains. Relying on over-current protection is only acceptable for bipolar-junction devices where the junction breakdown is reversible and non-cumulative.

In case (1) you just don't worry about power factor and accept that the diodes conduct only during top few percents of a cycle.

In case (2) you'll have to use 3-phase power and polyphase rectifier design to have acceptable power factor and diodes that conduct current around 60 degrees of the 360 degrees cycle.

Again, I don't have a specific knowledge about Bitfury's chips and their communication protocols, but some power electronics designs deal with 100% ripple by resetting the devices at 100Hz or 120Hz during the zero-crossings of the mains power. It probably wouldn't pertain to Bitfurries, but you still may consider modulating your mining clock rate during each half-cycle of the ripple. Over-clock when the chip are over-volted on the average and under-clock when the chips are under-volted on the average. The required additional power in the controller is next to nothing when compared with the power losses in the full, actively stabilizing regulators. Adjusting the clock rate several hundred times per second shouldn't be a problem for properly designed controller.

I'm sorry my first response took you for a noob. I simply didn't consider the case of (1), a design like one would do to settle a bet. In the past I had to deal with many people who were digital design experts but relatively ignorant in power electronics design. They would advocate type (2) designs with flaws obvious to anyone who had to experience beyond stabilized/regulated benchtop power supplies.

I did not think you are noob - I am sure you know how rectifier works. I see PFC ctrl much better idea:

1) PFC means stable op voltage, easy to tune, no efficiency drops
2) with current limiter you will dissipate lot of energy.
3) it is unclear if you want to filter rectified voltage, but from your posts it looks you would like to use unfiltered -> how do you make chips stable at low voltage parts of periods?
4) If you want to limit current at 2A, you will have about 78V@2A RMS at transistor to dissipate.

Still think PFC version is better. But wish you good luck, it would be really nice if you prove it can work.

To both 2112 and RadekG

The idea is exactly the opposite - use simple diodes rectifier and transistor current limiter.
I am not a noob and know how the rectifiers work and in the calculations above 220 * 1.4 is simplified for  220 * sqrt(2).
Many people said that it won't work and that's why this (crazy / hobby) project - to prove it does!

I have a working design at 24V DC and the built-in current mirror in the chips is working and balancing (almost) perfectly the voltage. I have made extensive test with the chips previously and this project will be a miner around the 55nm Bitfury chips, not a standard miner design. The chip survives 1.5V with proper cooling and it's voltage drop depends mostly on the current passing through it.
So transistor current limiter should be more than enough and 1.5V per chip is 420V AC, which won't happen and at that voltage the current is over 3A, while i will limit it to 1.5A or 2A max. This equals to about 0.88V per chip, because it's internal resistance when hashing is 0.44 Ohms based on my tests.

There are two other problems concerning me - the SPI speed (my next post) and the ripple/capacitor size (the next next post)

That could be fun, just remember active PFC is also a boost converter so your output voltage would be more like 350.

I think best what you can do is use PFC controller to stabilize voltage, keep power factor close to 1 and of course bypass huge capacitors.

I don't think that you understand how a rectifier works. 220V is an RMS voltage (root mean square). This means that unloaded bridge rectifier produces on output 220 * sqrt(2) or about 311V. The output under load will be lower depending on the exact design of your ripple filter.

You need to actively monitor angle of conduction in the rectifier to operate you mining string safely. This means that you can't use diodes in the rectifier but SCRs (thyristors) and actively control when to turn them on in each cycle (not difficult at 50Hz or 60Hz). For experiments (to learn) you can use diodes in the rectifier and an artificial resistive load (like incandescent light bulbs) in parallel with your string of chips.

Have fun!

Edit: In practice people using unregulated rectifiers use multi-phase rectifiers (typically 3 or 6 phases), not a single phase rectifiers. See comments about rectifiers in https://en.wikipedia.org/wiki/Polyphase_system .

Edit2: For fun (to play and learn) use a welding rectifier (with a transformer or an auto-transformer) for testing. Just remember to disable the arc-start circuitry, the one that briefly produces higher output voltage to make it easier to spark the arc for welding. You will need less chips in your string.

STEP 1 - determine the number of chips for the string based on voltage

The mains voltage here is 230V on average, but floating between 220V and 235V with absolute min 205V and absolute max 265V according to the specs.

The optimal voltage for the chip is 0.81V, below 0.62V (say 0.65V to be safe) it gets unstable and survives up to 1.5V, but a reasonable maximum to keep the losses low is 0.95V

For min 0.65V at 205V, there should be no more than ~440 chips ( 205 * 1.4 / 0.65 )
For max 0.95V at 265V, there should be not less than ~390 chips ( 265 * 1.4 / 0.95 )

OPTION 1 - the number of chips X: 390 < X < 440
OPTION 2 - the same but for the average range (220V - 235V): 346 < X < 473
OPTION 3 - optimal voltage at the average voltage: X = 397.5

The PCB is designed in panels with 4 hash-boards per panel and each hash-board consists of two rows 7 chips each, so the number chosen should be multiple of 7, but preferably 14 and best 56 (full panel)
From option 3 and full panels, there should be 7.1 panels.
The closest 7 panels are 392 chips
For lower power consumption with 8 panels - 448. That's more than 440 for the lowest voltage (205V), but it results in 0.64V per chip which is still OK.

I will order 8 panels for assembly to start with 448 chips and gradually test 434, 420, 406 and 392, but there is one more thing to consider for the number of chips ...

I am looking for some old 55nm Bitfury chips (Rev 1 or 2) to build a direct 220V string. If you have some, please post here or PM me.

I know they are not profitable anymore and it is a bit late for fireworks , but still have some PCBs printed and would love to try that crazy idea.

EDIT:
Thanks guys!
Got around 500 chips, which should be enough for the string and some replacement chips (after the fireworks)

I will report about the development in the following posts if it is of interest for others.