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Topic: 750 KH using 5mW? (Read 1510 times)

sr. member
Activity: 462
Merit: 250
It's all about the game, and how you play it
November 17, 2011, 08:32:38 PM
#6
Its a research chip to compare various SHA3 implementations, its not a commercial product. Its also not an FPGA, but an asic. But if you want,  "Free SHA-3 sample chips are available upon request. ". Go right ahead and start mining at 5mW Smiley

i wonder how many sapmles we're allowed
donator
Activity: 1218
Merit: 1079
Gerald Davis
November 17, 2011, 06:26:49 PM
#5
Scroll down to page 14. For 512 bit blocks it says throughput is 1.51 Gbps @200 Mhz . Next page reveals a power consumption of 5mW.
So we are looking at 0.75 MH/s for 5mW ?
Scale that up and you get 750MH for 5W and still have a chip thats pretty damn small.

Actually I think it is 1.5MH/s @ 5mW.

Right?

1.51 Gbps = 1510Mbps / 512 bits per clock = 2.95MB/s.  Bitcoin megahash is actually 2 SHA-256 hashes (2 blocks) so 2.95/2 ~= 1.5MH/s @ 5mW.

1.5MH/s / 0.005W = ~300 MH/W.
hero member
Activity: 518
Merit: 500
November 17, 2011, 06:20:56 PM
#4
Its a research chip to compare various SHA3 implementations, its not a commercial product. Its also not an FPGA, but an asic. But if you want,  "Free SHA-3 sample chips are available upon request. ". Go right ahead and start mining at 5mW Smiley
hero member
Activity: 518
Merit: 500
November 17, 2011, 02:31:23 PM
#3
I uploaded it to google docs, hopefully you can access that:
https://docs.google.com/document/d/1l7nHZr4OeXZZwt9xbbDovmIv4q9RtM3X6tFsRWv4q5w/edit

Then Ill let you provide the correct arithmetic Smiley
legendary
Activity: 2128
Merit: 1073
November 17, 2011, 02:23:06 PM
#2
Can you write down your arithmetic that computed 750kH/s? Do you assume same chips looping data back to itself or a pair of chips working as a pipeline?

I see a design with 200MHz clock, 16-bit wide streaming data input/output and 68 cycles of latency. 512-bit width of block shouldn't matter, this is an internal detail. From my place I can't get the #1 citation in this paper: "A hardware interface for Hashing Algorithms".
hero member
Activity: 518
Merit: 500
November 17, 2011, 03:48:14 AM
#1
Edit: got it wrong by a few orders of magnitude. Corrected.

These guys have built a test chip essentially for testing SHA-3, but they also included an SHA 2 core:
http://rijndael.ece.vt.edu/sha3/sha3chip.html

The chip is just 5mm2 using standard cells 130nm process, the SHA2 core is only a tiny percentage of that. Now look at the data sheet:

http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf

Scroll down to page 14. For 512 bit blocks it says throughput is 1.51 Gbps @200 Mhz . Next page reveals a power consumption of 5mW.

So we are looking at 0.75 MH/s for 5mW ?

Scale that up and you get 750MH for 5W and still have a chip thats pretty damn small.
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