ASICs do not have uniform speeds across technology nodes. A SHA-2 core operates close to 500 MHz at 45 nm depending on architecture. The entire speed of the chip depends on the architecture, not just the technology node.
A 333 MH/s chip at 65 nm is going to be smaller, and thus probably cheaper than the 4 GH/s chip. In bulk terms, it is usually not cheaper to buy 12 of them. Underclocking generally is more economical than redesign for a chip manufacturer.
Topic: ASIC chip info request. (Read 541 times)
In my reading I see talk of 110nm, 65nm, 55nm and 28nm chips. Has anyone made up a chart of all the different sized chips and the speeds they operate at?
I've also been trying to understand the complexity... ie: is it easier to make a 333MH 65nm chip as compared to a 4GH 65nm chip? Is it cheaper? Since more lower clocked chips are needed for the same output, in bulk terms can you get 12x 333MH speed chips for less than 1x 4GH ones?
Some companies are going to underclocked chips to save power, is this more economical than redesigning the chips to meet power requirements?
Thanks in advance for your responses.
I've also been trying to understand the complexity... ie: is it easier to make a 333MH 65nm chip as compared to a 4GH 65nm chip? Is it cheaper? Since more lower clocked chips are needed for the same output, in bulk terms can you get 12x 333MH speed chips for less than 1x 4GH ones?
Some companies are going to underclocked chips to save power, is this more economical than redesigning the chips to meet power requirements?
Thanks in advance for your responses.
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