“Getting revenues from shipment can be defined as ‘commercialization’, but ASIC is a relatively simple kind of chip to produce, in terms of architecture,” Chen remarked. Analyst John Wang from Digitimes emphasized that the yield from Samsung’s 3nm GAA process remains low. Consequently, Wang believes the tech giant aims to attract a broad customer base to refine its procedures and enhance yield. The report from Techinsights concludes by noting the uncertainty surrounding the use of Samsung’s 3nm chips in any additional hardware devices in the market today.
Does not surprise me. As I've often said in the past, mining ASIC's are excellent for refining bleeding-edge chip production processes: being dirt simple circuits and highly tolerant of process variability translates into them being the perfect high-volume test bed for advanced node sizes. Despite initial low yields it still provides the Foundries with revenue from any usable chips and gives them process data needed so more complex chips can be produced as the production processes become more refined giving higher yield of usable chips.
The folks that paid TSMC, Samsung & Global Foundries for research into making smaller node sizes even
possible were Apple, Broadcom, Cisco, Micron, NVIDIA et al. Thing is, research leading to actually being able to build & implement everything required is one thing, fine tuning everything to be able to produce the
billions of gates & their interconnections present on each chip with 0-errors and repeat it thousands of times per-wafer is a whole `nother story. Ref
https://en.wikipedia.org/wiki/Transistor_count for insight into the phenomenal number of gates in them these days... From that article:
The highest transistor count in a consumer microprocessor is 134 billion transistors, in Apple's ARM-based dual-die M2 Ultra system on a chip, which is fabricated using TSMC's 5 nm semiconductor manufacturing process.
Only actually producing hundreds of thousands of lower complexity test chips in the brand sparkly-new production environment lets you do that. The main users of the chips are not going to directly pay for those massively expensive runs of test chips: enter mining chips to let the Foundries figure it out before risking far more complex and valuable chips.
TSMC did the exact same thing for that same reason using Bitmain and Canaan chips as the guinea pigs for their development of the 28/27nm (S1) thru 5nm (S19) production nodes. Samsung previously did this with Canaan's ill fated A941 which was the 1st miner to use the 10nm node.