Topic: ASIC Miner's Efficiency , Where Does it Stop? (Read 514 times)

well it likely does 16 not 15 still we could get under ten 🔟 watts down the road.

If I manage  to live long enough maybe I will see 8 or 9 watts.

Say 2031.

i would bring up this interesting topic again, because since the announcement of the s21 series, the efficiency value has continued to rise and now, for the first time, there is also a 1x in the w/th values
the s21 pro delivers a massive 234 th/s at 3510 watts - that's ~15w per terahash. and in my opinion we will break through 10w/th before the end of this decade

Does not surprise me. As I've often said in the past, mining ASIC's are excellent for refining bleeding-edge chip production processes: being dirt simple circuits and highly tolerant of process variability translates into them being the perfect high-volume test bed for advanced node sizes. Despite initial low yields it still provides the Foundries with revenue from any usable chips and gives them process data needed so more complex chips can be produced as the production processes become more refined giving higher yield of usable chips.

The folks that paid TSMC, Samsung & Global Foundries for research into making smaller node sizes even possible were Apple, Broadcom, Cisco, Micron, NVIDIA et al. Thing is, research leading to actually being able to build & implement everything required is one thing, fine tuning everything to be able to produce the billions of gates & their interconnections present on each chip with 0-errors and repeat it thousands of times per-wafer is a whole `nother story. Ref https://en.wikipedia.org/wiki/Transistor_count for insight into the phenomenal number of gates in them these days... From that article:
Only actually producing hundreds of thousands of lower complexity test chips in the brand sparkly-new production environment lets you do that. The main users of the chips are not going to directly pay for those massively expensive runs of test chips: enter mining chips to let the Foundries figure it out before risking far more complex and valuable chips.

TSMC did the exact same thing for that same reason using Bitmain and Canaan chips as the guinea pigs for their development of the 28/27nm (S1) thru 5nm (S19) production nodes. Samsung previously did this with Canaan's ill fated A941 which was the 1st miner to use the 10nm node.

Nice find. That unit will be very nice  the M56s++

Microbt Unveils New Whatsminer Bitcoin Mining Rig With 320 TH/s, Setting New Standard for Hashpower

https://news.bitcoin.com/microbt-unveils-new-whatsminer-bitcoin-mining-rig-with-320-th-s-setting-new-standard-for-hashpower/

Microbt’s hydro-cooling ASIC mining rig, the M53S++, delivers an unrivaled hashpower output in the industry today. The Whatsminer M53S++ reaches a staggering 320 TH/s — a whole 65 TH/s greater than Bitmain’s Antminer S19 XP Hydro, the previous top BTC miner in terms of hashrate.



But I only see 5nm not 3nm in my link.

So I am not sure which link is correct. The gear claims to be 22 watts which is a big issue.

22 watts x 320 th immersion m56s++ = 7040 watts which means 8 gauge wires and  40 amp circuit. or maybe 2x  20amp circuits to run it.

the air-cooled M50s++ doing 150th at 22 watts is 3300 watts not much of an issue.

Apparently Whatsminer is already using 3nm from Samsung.

https://news.bitcoin.com/samsungs-3nm-gaa-chip-discovered-in-microbts-next-gen-bitcoin-mining-rig/

I have to go see if I can find the lecture, but it was from some IBM engineer a couple of years ago, and although not about mining he made a really good point that there ARE many more efficient ways of doing some things with processor and other designs for them BUT the problem is you have to sell them.

It's easier and cheaper to put a bunch of lower power need and lower speed chips from the last generation that you made with the newer generation processes on a board to get the same speed as a newer and faster current generation chip.

It at times can even be more energy efficient because even if you DO need more power to drive the older chips you can do some other things that make heat removal [he said never call it cooling since you are not actually cooling the chips just taking the heat away from them] since you have more surface area so those requirements drop and the circuitry to drive them is more spread out. The example he used was put a space heater in a small room and see how fast the temperature rises then do the same thing a room 3 x the size.

The above is all well and good.....

BUT, in the world as he put it, space for servers costs money so businesses want density. Marketing & sales can't sell last generation things even if they are betting since the competition can point to theirs that are newer even if not better. And so on.

Same thing more or less here.

-Dave

For mining more chips and under clock will rule.

to be honest 3nm is already a big achievement in my opinion. Even Corona Virus is way bigger than the current chipset size

"Upon analysis of negative-stained SARS-CoV-2 articles by electron microscopy, different researchers have had varying results, but the diameter of the virus has been found to range between 50 nm to 140 nm" - https://www.news-medical.net/health/The-Size-of-SARS-CoV-2-Compared-to-Other-Things.aspx

Tho what will gonna happen if chip stop shrinking  are the size of the CPU will getting bigger like CPU server did ?

3nm may be the end of the line.

https://www.ft.com/content/fbf52ede-e1a9-4797-9e52-3f80a7d855d9

but the article above claims 2nm for sure maybe lower.

There is a limit much like gasoline does not get 1000 miles a gallon.

chips will stop shrinking.

so 2nm is likely
1.5 nm is maybe
1.0 nm is iffy.

in terms of mining.
5nm is 20 watts
3 nm say 16 watts.
2 nm maybe 12 watts.

when and if we bottom out say 2nm the chips will be cheaper and cheaper and cheaper since the bottom was met.so ten years at the smallest size will make chips cheap.

thus more chips and underclock will rule.

maybe we see a 5 watt machine one day.

Just a quick search on the TSMC website that they already created 3nm chip process meaning this is crazy. maybe a more efficient ASIC is still in development.

"TSMC’s 3nm technology (N3) will be another full node stride from our 5nm technology (N5), and offer the most advanced foundry technology in both PPA and transistor technology when it is introduced. N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology. N3 technology development is on track with good progress. N3 technology will offer complete platform support for both mobile and HPC applications, which is expected to receive multiple customer product tape-outs in 2021. In addition, volume production is targeted in second half of 2022." - https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm

S7 vs S9 is a massive improvement, the chip size is 28nm vs 16nm, and then you got Asicboost (we don't know if they had that on the s7 or not, but we don't have any figures to compare anyway), so an S9 without Asicboost it would be more like 1500w and 14th instead of 1250-1280 and 14th, which in self is a very large improvement.


Is that due to technical constraints or more like economic constraints?  I also doubt we get there anytime soon, but I'd guess it's more of the cost than the ability, I mean if you could sell a 15w/th or 20w/th gear like there is no tomorrow, why increase the cost? in fact, I think as it stands right now Bitmain can probably make S19 xp hash at 16-17w/th, and MicroBT can make M50s++ hash at 15-16w/th, but the cost would be extraordinarily higher and will probably not have any market value with the current price and difficulty.

well considering  that s7 to s9 was 4.7th at 1300 watts and s9 was 14.1th at 1300 watts about 3x the hash for the same power the drop off was huge
since the s-9 came out.

I do not see 10 watt gear anytime soon.

It's pretty amazing how we keep climbing up the efficiency ladder, taking Bitmain is an example and ignoring everything prior to AsicBoost because that was a game changer, I gathered the small piece of info below ignoring all the "T" models and some variation of some models that I don't see relevent.


I have little to no knowledge of semiconductors design or manufacturing, but it doesn't seem like we still have too much room for improvement on the chip level, so maybe they'd start putting more chips on a single board, lowering the frequency and voltage to achieve the best efficiency at the expense of price, with more focus on the firmware level.

Where do you see mining efficiency in the coming few years, any chance we drop below 10w/th? I am interested in hearing your thoughts.