FPGA waste a lot of internal gates/latches/buffers/whatever to implement a design. So ASICs can do what a FPGA does, but not the way around in most cases.
For mining, you want to use every gate available to perform massively parallel computations. So the design of the ASIC has to be made specially for that ASIC and will not just be a port of what was done for the FPGA.
The other side of the (bit)coin being : designing the function for the ASIC is 10% of the work. simulation and most specifically Thermal response simulation is the hard part. You pretty well can come up with a design that behave very poorly thermically speaking once you have the final chip, and which finally runs at 1/10th of the originally designed speed.
And redoing it is a no-go, since it costs all that money again.
So, ..., big surprises are expected ...