Type of microscope?
Chinese optical metallographic microscope BM-158J with 5 mpix USB camera. (~60 shots stitched for 1 large photo)
http://3.14.by/en/read/microscope
Awesome work
Topic: Avalon chip microscope photos revealed (Read 2282 times)
Chinese optical metallographic microscope BM-158J with 5 mpix USB camera. (~60 shots stitched for 1 large photo)
http://3.14.by/en/read/microscope
Awesome work
Type of microscope?
Chinese optical metallographic microscope BM-158J with 5 mpix USB camera. (~60 shots stitched for 1 large photo)
http://3.14.by/en/read/microscope
Type of microscope?
[...]
I've cut the whole reply just to say "thanks", it's very interesting!
I'm a bit "old fashioned" and I admit that I tried to figure out using the information I know about CPUs.
Quote
Any links on who to ask to get a sample chip from them?
Inaba/Josh maybe
Interesting. First time to know somebody is reverse engineering Chinese product.
That's second time for me Recently I was looking into cheapest (5$ delivered) Chinese webcam - and it's the same engineering & logistics miracle (how on earth they managed to squeeze it all in 5$?
) as bleeding-edge 22nm products. 
Interesting. First time to know somebody is reverse engineering Chinese product.
Great Work.
Anyone knows if the Avalon chips project is a sort of "hard copy" of the Icarus FPGA? It can explain why it has a structure like that (from the little that I know, the FPGAs are basically the same, just bigger and programmable).
No, it's not a "hard copy" of FPGA. It might be based on the similar algorithm implementation, but that's the extent of similarities. By the way it's probable that you can't go lower than 110nm production process if you want to keep temperatures under control and maintain the QFN package. That's why BFL had to redesign the chip and use the FCBGA package, with that shiny upper surface (very vulnerable too, they have something of the old AMD Athlon Palomino CPUs).
That is not exactly true. In CMOS you can always lower power consumption by an order of magnitude by lowering supply voltage & clock, and then compensate for that by using more chips (power drops non-linearly, so there is a benefit).Borrowing information from other products (i.e. systems on a chip like the ARM Cortex) 28nm is often a "die shrink" of an existing 32nm chip, so if Orsoc/KNC has already been able to make a 32nm chip it's not hard to think that the first prototypes will use this bigger (and less efficient) die, doing the shrink when everything is -almost- fine. It "should be" better, I still remember what happened when Intel launched the P4 Prescott series...
You cannot simply shrink the die on the modern processes as it was possible at the times of 350-800nm technologies. You must redo almost everything - there is just way too much constraints, and too much changes with this "mere" 14% shrink. I forgot to mention that the BFL chip is made by Global Foundries with a production process of 65nm.
Any links on who to ask to get a sample chip from them?
interesting to see a damaged chip
Anyone knows if the Avalon chips project is a sort of "hard copy" of the Icarus FPGA? It can explain why it has a structure like that (from the little that I know, the FPGAs are basically the same, just bigger and programmable).
By the way it's probable that you can't go lower than 110nm production process if you want to keep temperatures under control and maintain the QFN package. That's why BFL had to redesign the chip and use the FCBGA package, with that shiny upper surface (very vulnerable too, they have something of the old AMD Athlon Palomino CPUs).
Borrowing information from other products (i.e. systems on a chip like the ARM Cortex) 28nm is often a "die shrink" of an existing 32nm chip, so if Orsoc/KNC has already been able to make a 32nm chip it's not hard to think that the first prototypes will use this bigger (and less efficient) die, doing the shrink when everything is -almost- fine. It "should be" better, I still remember what happened when Intel launched the P4 Prescott series...
I forgot to mention that the BFL chip is made by Global Foundries with a production process of 65nm, and it seems they had "some problems" in the past...
By the way it's probable that you can't go lower than 110nm production process if you want to keep temperatures under control and maintain the QFN package. That's why BFL had to redesign the chip and use the FCBGA package, with that shiny upper surface (very vulnerable too, they have something of the old AMD Athlon Palomino CPUs).
Borrowing information from other products (i.e. systems on a chip like the ARM Cortex) 28nm is often a "die shrink" of an existing 32nm chip, so if Orsoc/KNC has already been able to make a 32nm chip it's not hard to think that the first prototypes will use this bigger (and less efficient) die, doing the shrink when everything is -almost- fine. It "should be" better, I still remember what happened when Intel launched the P4 Prescott series...
I forgot to mention that the BFL chip is made by Global Foundries with a production process of 65nm, and it seems they had "some problems" in the past...
The most interesting part for me is the final conclusion in the blog about Avalon density.
Is it possible to compare it to expected cell-based 28nm chip from KNC? I mean in terms of performance/consumption?
Is it possible to compare it to expected cell-based 28nm chip from KNC? I mean in terms of performance/consumption?
Rough back-of-the envelope calculations shows that 28nm product must be ~10-15 times more energy efficient, dumb implementation could impact it by a factor of at least 2-3.
So we are talking about ~5 times more Mhash for same consumed power.
But even if it says "cell based", I would not expect straightforward naive implementation given that amount of labor for full-custom bitcoin-chip design does not differ very much for 110nm/65nm/28nm.
Mmmm, ASIC pr0n. 
The most interesting part for me is the final conclusion in the blog about Avalon density.
Is it possible to compare it to expected cell-based 28nm chip from KNC? I mean in terms of performance/consumption?
Is it possible to compare it to expected cell-based 28nm chip from KNC? I mean in terms of performance/consumption?
BarsMonster, are you doing those awesome reverse-engineering microscope photos on the blog?
Yep, that's me.
BarsMonster, are you doing those awesome reverse-engineering microscope photos on the blog?
Awesome, now this is what I cann ASIC-porn!
Ente
Awesome, now this is what I cann ASIC-porn!
Ente
Great photos!
Slightly damaged chip was extracted from live mining rig (thanks for the chip goes to our fellow forum member needbmw):
http://s.zeptobars.ru/avalon-chip.jpg
http://s.zeptobars.ru/avalon-Si.jpg
http://zeptobars.ru/en/read/avalon-bitcoin-mining-unit-rig
PS. I am open to make photos of any other custom bitcoin chips. Bitfury is next on the train. BFL, anyone?
http://s.zeptobars.ru/avalon-chip.jpg
http://s.zeptobars.ru/avalon-Si.jpg
http://zeptobars.ru/en/read/avalon-bitcoin-mining-unit-rig
PS. I am open to make photos of any other custom bitcoin chips. Bitfury is next on the train. BFL, anyone?
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