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Topic: - Avalon chips - timing REPORT signals - (Read 754 times)

sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
May 31, 2013, 01:44:50 AM
#1
Is someone with an Avalon board willing to put a scope probe
on the REPORT_N/REPORT_P lines (pins 17 and 18) and observe
the timing of the signal? Interrested in:

- Up-going edge schape (it's a pulled-up pinch/release line,
   could have RC characteristics).
- Clock period and duty cycle of 1 bit period.
- Length in bits of the sent data.

Will pay a BTC 0.10 bounty for the first, clear scope screen hardcopy.

PM me please,

intron
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