Hi,
Read the datasheet of the Avalon 'A3256-Q48 SHA256 Processor'
and to me there are few things not really clear about this
REPORT_x pins. They seem open drain outputs, there are
pull-ups required, so it looks like the REPORT_x lines of all
Avalon chips can be tied togeter to form a party-line. This
makes sense as it saves a lot of pins on the microcontroller.
But if so, how are contentions resolved when two or more
chips have found a golden nonce at the same time?
Any ideas anyone?
intron
Read the datasheet of the Avalon 'A3256-Q48 SHA256 Processor'
and to me there are few things not really clear about this
REPORT_x pins. They seem open drain outputs, there are
pull-ups required, so it looks like the REPORT_x lines of all
Avalon chips can be tied togeter to form a party-line. This
makes sense as it saves a lot of pins on the microcontroller.
But if so, how are contentions resolved when two or more
chips have found a golden nonce at the same time?
Any ideas anyone?
intron
I haven't looked at the datasheet myself yet, but maybe they figure that won't be a problem since the chances of that happening are extremely slim.
Could very well be that way. I'll try to calculate the changes
of a collision and thus lost data.
intron