Topic: BM1366 overheating (Read 161 times)

Thats great, good luck getting it going properly.

Just another note while I think of it.

From experience with the BM1397. I can tell you they are quite sensitive to core voltage variations. For example with the BM1397, it will hash at 450Mhz when the core voltage was 1.50 but not when the core voltage was 1.45V just 50mV was the difference between it working and not. Reducing the clock to 400Mhz it would hash at 1.475V and above at 350Mhz it would hash at 1.45V and would not hash at all at lower clock speeds.

So, if I were you I'd start with a nominal clock rate ~400Mhz and trim the core voltage low say 1.05V and step it up 50mV at a time resetting the device each time to see if you can get it to hash or perhaps try a lower clock speed to start with.

Anyway, good luck.

Yeah, I managed to detect one chip on the board. FINALLY :-).

Problem seems that the chip wasn't soldered properly. For this version, I first "reballed" the chip itself with some solder paste and then soldered it on the PCB. And now, I have a communication. The chip is responding!

But somehow, the current is very low and the chip seems not really hashing.

But I'm really happy that I can now talk to the ASIC ;-). Thank you all for your help. I really appreciate it!

I did not look at your schematics, but you can (and should if you want to save cost) use Vcore for 1.2V. I have all my miners converted to 1.2V this way. Also you can make the 0.8V with a simple resistor divider from the Vcore (any voltage between 0.7V and 0.95V will work in my testing). The asic draws less than 10mA on the 0.8V line.
(edit glanced at the schematics..)
For testing i would tie the BI from the first asic to ground and the RI to 1.2V, so the asic will always respond to (correct) commands. If you are going to use level shifters between the asics (I think you need them if you use 1.2V as Vdd_IO, maybe not for 1.8V) you can skip level shifting the clock and just use a capacitor of 10nF.
(another edit)
The clock must be present on the CLKO line.
If you do not have a level shifter on the NRST line you are keeping the 2nd asic reset, thus it will consume less power, resulting in unequal voltages over the domains.
I don't think debugging the circuit without voltage shifters will be easy. As long as you do not initialize the asics you should at least get a response on a read-register command, but anything more will be difficult.

If you're confident that the hardware is correct and you have no assembly issues that can only leave one thing.

Software!

Good luck with that, its not my cup of tea to be honest.

I think you'd best talk to the guys that designed the Bitaxe software and see if they have any suggestions.

I'm not sure I can be much more help.

Good luck...

Thanks for reviewing my schematics.

I have now reworked a few things.
1. I supply the VDDIO_18 pin with 1.2V (using the chips power supply)
2. Checked if the crystal oscillator is still working with 1.2V and it is.
3. 0.8V supply is generated from the 1.2V. So, if the power supply is switched of, the VDDIO supply is also off.

I think from the electronic point of view, I'm probably using the chip well within its specs.

But I still don't get any response from the ASIC.

I'm open for every other clue 

I don't know anything about the Bitaxe software or its intricacies. It could very well be that it is not compatible with the AL version as you've suggested and it may be looking for a particular chip version ID, you'd best ask the design group behind Bitaxe for assitance on that front.

I've had a quick look at your schematic, couple of notes:-

1. U6 level transaltor pin 8 and pin 11 should not be left to float, this is bad practice and could lead to metastable states on the IO. Best to tie pin 8 and 11 low via 10K resistor.

2. X1 enable pin is float according to your schematic, again bad practice, not all oscillators have internal pull-ups on the enable pin. I'd suggest fitting R29 10K. Without it there's no guarantee the clock will be stable.

3. Not sure this will make much difference, but the schematic for the S19K where BM1366 is used shows C57,C59,C61,C62 and C56, C60 as 100nF not 1uF.

4. to reduce power dissipation in U7 and U8, you may want to run them from 3V3 instead of 5V, while there's not much load on either the 0V8 or 1V8 supplies it makes sense to minimise power losses where possible.

5. Cant vouch for your power supply design since you omitted the schematics for that. I presume you've measured it under load with an oscilloscope and that it is stable and has minimal ripple and noise?


Other than the points above, I can't see a good reason why you cant communicate with the two devices in the chain. Which kind of suggests there's software involved somewhere along the line.

I presume you've monitored the TX and RX lines to see what data is being sent and if there is any comms back from the ASICs at all?

The last thought is power sequencing, I think VDD1 needs to be active before applying 0V8 and 1V8 since they are referenced to a virtual ground point when the parts are DC stacked, so you might want to tie the enable pins from U7, U8 to the powergood output on your VDD DCDC converter.

Just an additional information. I bought BM1366AL chips from NBTC. Could that be a problem? Because on discord I have seen that someone else has problems with the AL variant to be detected on Bitaxe Hex.

Are there any official Infos available?

The first page contains the modules and how they are wired. It is important to note, that I'm right now testing PCBs with just the first two ASICs assembed. The level converter and the second 2 ASICs are not assembled. And VDD1 is now directly supplied with 1.2V from the power module (TPS546B24A).

https://nextcloud.emicrotec.at/index.php/s/NmR9skFPHfPaaLW

Can you post a bmp or pdf of your schematics its impossible to debug without more detail.

Thanks for the reply. I think 2.4V is just fine because I have 2 of them in series and each chip should get its 1.2V operating voltage. But as I said, I measured an unequal distribution of the voltage.
Regarding cooling and the heatsink, I think you are totally right. I powered up the first board because I thought the chips would just getting warm as long as I don't let them hash. But I think I was wrong with that.

I have now assembled a couple more of my boards but on none of them I can detect the ASICs. I always get the message 0 ASICs detected but expecting 4.

And because of not getting any communication with the ASICs, I decided to have a board assembled with just 2 ASICs in parallel and supply them with 1V and 1.2V. But I have still the same issue that I don't get anything back from the chip and the chain is not detected.

I'm sending some data to the ASICs with 115200 baud on the UART with 1.8V level. The BI (busy input) pin is low. The 25MHz oscillator is running.
So, I'm slowly running out of ideas what I can do to get it up and running.

Has anybody an idea what else I can test?

Thanks!

I believe that the 2.4 volts you are providing is beyond the max voltage for this chip. Why did not you start with the lowest voltage possible, or 0.8v, and gradually increase it based on the ASIC temperature?

Plus, without a heatsink and fan, how do you cool the chip?
I believe you cook them and it died from overheating.

If you did manage to get them to start without a heatsink they're likely dead within seconds.

12Watts into an 8x8 package = very hot very quick. Most semiconductors have a maximum operating junction temperature of 125C, they tend to fail around 150C

Speaking from experience with BM1397, without a heatsink attached once configured and running they reach 85C in less than a second, so junction failure is a fraction of a second away.

Best guess is you've destroyed the ASICs by attempting to run them without adequate cooling.

Hello.

Maybe, some of you can help me out. I designed a board with 4x BM1366 ASICs based on the Bitaxe and Bitaxe Hex.
The last couple of days, I tried to get it up and running, but I get no communication with the ASICs itself. The controller is sending data to it, but nothing is coming back.

What I observed is, that the current consumption is increasing when the chips are getting warm. And at the beginning, I had no heat sink (or a very simple one) on it. Could it be that the ASICs got damaged because of too much heat and current?
Additionally, I'm powering the 4 ASICs with 2.4V because 2 of them are in parallel an then they are in series with the other 2. So, overall core voltage need to be 2.4V. But what I see is, that the voltage is not equally distributed over the ASICs. The first 2 ASICs have 0.8V and the bottom 2 are supplied with 1.6V. May this be a sign that the ASICs are damaged?

Should the clock signal be available on the inverted CLK output pin of the ASIC? Because, I don't see anything there.

I hope someone can help me out.

Thanks,
Andreas