Author

Topic: cluster FPGA dev board (possible) (Read 582 times)

newbie
Activity: 28
Merit: 0
April 19, 2013, 03:01:57 AM
#11
I am also studying the manual book on fpga.
and i'm waiting for your simple tutorial

thanks signus

Manual book? Which book? I can probably recommend you a better one. There are tons of books about FPGA development and programming in Verilog.

It doesn't look like anybody has used this dev board to my knowledge. I can't write the Verilog without a board to test with, and I don't have the extra money laying around. But I'll write you a tutorial to get you started with learning Xilinx and connecting it, and if I find anything for that chip family, I'll put it in there too.

Might have to wait a day or two.
newbie
Activity: 14
Merit: 0
April 19, 2013, 02:48:42 AM
#10
Quote
here this pic i.imgur.com/jUAw0Lb.jpg
Im newbie for using FPGA

Just so you know, there's a USB port directly next to the Ethernet port.

You have to get Xilinx ISE. You can get a Student Evaluation Version for free. Then you have to upload Verilog code to the board via USB. If somebody else hasn't done so for this FPGA family, you have to write or modify the code for a similar chip family.

I'll look to see if anybody has used that board, but I think you might get a 100-250MH/s a chip for those. If anybody has used that board, I'll write up a simple tutorial for you.

So you got these handed off to you then?


I am also studying the manual book on fpga.
and i'm waiting for your simple tutorial

thanks signus
newbie
Activity: 28
Merit: 0
April 19, 2013, 02:11:32 AM
#9
Quote
here this pic i.imgur.com/jUAw0Lb.jpg
Im newbie for using FPGA

Just so you know, there's a USB port directly next to the Ethernet port.

You have to get Xilinx ISE. You can get a Student Evaluation Version for free. Then you have to upload Verilog code to the board via USB. If somebody else hasn't done so for this FPGA family, you have to write or modify the code for a similar chip family.

I'll look to see if anybody has used that board, but I think you might get a 100-250MH/s a chip for those. If anybody has used that board, I'll write up a simple tutorial for you.

So you got these handed off to you then?
newbie
Activity: 14
Merit: 0
April 19, 2013, 01:46:54 AM
#8
Well you are using the Virtex-5 FPGA Family, but what Development Board are you using?

I don't know that anybody has developed a FPGA bitstream for Ethernet on the boards, but RS-232 is way too slow to be of any use. You can program it via RS-232, but it would have to be written to operate over the network.

Could you provide a picture of the dev board? Please provide multiple views so we can see all the GPIO.

And did you buy these up or did you happen to run across some spares?

I want to try to usb, but I think the result is not optimal

Why do you say not optimal? What do think will be the deficiency? Remember mining is not about IO bandwidth, at least on the mining rig side.

I think he has an older development board, and I'm assuming they've never done anything with FPGA's before.

here this pic i.imgur.com/jUAw0Lb.jpg
Im newbie for using FPGA
newbie
Activity: 28
Merit: 0
April 19, 2013, 01:36:51 AM
#7
Well you are using the Virtex-5 FPGA Family, but what Development Board are you using?

I don't know that anybody has developed a FPGA bitstream for Ethernet on the boards, but RS-232 is way too slow to be of any use. You can program it via RS-232, but it would have to be written to operate over the network.

Could you provide a picture of the dev board? Please provide multiple views so we can see all the GPIO.

And did you buy these up or did you happen to run across some spares?

I want to try to usb, but I think the result is not optimal

Why do you say not optimal? What do think will be the deficiency? Remember mining is not about IO bandwidth, at least on the mining rig side.

I think he has an older development board, and I'm assuming they've never done anything with FPGA's before.
newbie
Activity: 19
Merit: 0
April 19, 2013, 01:32:45 AM
#6
I want to try to usb, but I think the result is not optimal

Why do you say not optimal? What do think will be the deficiency? Remember mining is not about IO bandwidth, at least on the mining rig side.
newbie
Activity: 14
Merit: 0
April 19, 2013, 01:30:37 AM
#5
Not optimal? Every FPGA dev board uses USB. That's how cgminer or bfgminer and the like connect to the FPGA.

Either use 4 USB ports on your computer or get a powered USB hub. Don't go cheap, a bad hub can burn out the USB ports.


Out of curiosity, how did you get your hands on these boards?

this board there 10/100/1000 Ethernet PHY and RS-232 serial port
newbie
Activity: 28
Merit: 0
April 19, 2013, 01:20:07 AM
#4
Not optimal? Every FPGA dev board uses USB. That's how cgminer or bfgminer and the like connect to the FPGA.

Either use 4 USB ports on your computer or get a powered USB hub. Don't go cheap, a bad hub can burn out the USB ports.


Out of curiosity, how did you get your hands on these boards?
newbie
Activity: 14
Merit: 0
April 19, 2013, 12:17:48 AM
#3
I'm not sure what you mean exactly. However as a guess -> I am not familiar with these boards.

This is all on a Unix/Linux system. Get a USB hub. Connect them all to the USB hub via USB connections. Run cgminer with the relevant FPGA support compiled in an point them to  your USB ports. With cgminer pointing to a pool of some sort and configured for with your pool login/miner details and off you go.

I'm sure somebody will correct my mistakes and or oversights.

I want to try to usb, but I think the result is not optimal

for detail board
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,819&Prod=GENESYS
newbie
Activity: 19
Merit: 0
April 19, 2013, 12:14:41 AM
#2
I'm not sure what you mean exactly. However as a guess -> I am not familiar with these boards.

This is all on a Unix/Linux system. Get a USB hub. Connect them all to the USB hub via USB connections. Run cgminer with the relevant FPGA support compiled in an point them to  your USB ports. With cgminer pointing to a pool of some sort and configured for with your pool login/miner details and off you go.

I'm sure somebody will correct my mistakes and or oversights.
newbie
Activity: 14
Merit: 0
April 19, 2013, 12:07:13 AM
#1
I have 4 FPGA Virtex-5 FPGA Development Board . and i want cluster all , anyone know how to do it?
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