What software do you use to do that?
DC 
Topic: DIY ASIC miner chip in 0.18um CMOS, report (Read 1360 times)
What software do you use to do that?
It seems the reason for high power consumption has found, which is the designkit problem.
Hi Geeks,
I have tried to synthesize the miner ASIC using opensourceFPGA project source code.
Now I have finished the first synthesizing working flow( running for 18 hours!) and I would like to share the result. Any comment is welcome!
It seems the area and power consumption are toooo high compared with commercial chips.
Library: 0.18um standard digital CMOS
Fully unrolled design, 1clk/hash.
System clock: 166MHz.
hash rate: 166MHps
*******************area report*********************
Number of nets: 321497
Number of cells: 314029
Number of references: 216
Combinational area: 5414138.137791
Noncombinational area: 4252350.976124
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 9666489.113914
Total area: undefined
*******************Timing************************
data arrival time 5.82
clock clk (rise edge) 6.00 6.00
clock network delay (ideal) 0.00 6.00
library setup time -0.18 5.82
data required time 5.82
--------------------------------------------------------------------------
data required time 5.82
data arrival time -5.82
--------------------------------------------------------------------------
slack (MET) 0.00
*******************Power************************
Cell Internal Power = 2.5293 W (68%)
Net Switching Power = 1.1864 W (32%)
Cell Leakage Power = 42.3871 uW
---------
Total Dynamic Power = 3.7157 W (100%)
************************************************
I have tried to synthesize the miner ASIC using opensourceFPGA project source code.
Now I have finished the first synthesizing working flow( running for 18 hours!) and I would like to share the result. Any comment is welcome!
It seems the area and power consumption are toooo high compared with commercial chips.
Library: 0.18um standard digital CMOS
Fully unrolled design, 1clk/hash.
System clock: 166MHz.
hash rate: 166MHps
*******************area report*********************
Number of nets: 321497
Number of cells: 314029
Number of references: 216
Combinational area: 5414138.137791
Noncombinational area: 4252350.976124
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 9666489.113914
Total area: undefined
*******************Timing************************
data arrival time 5.82
clock clk (rise edge) 6.00 6.00
clock network delay (ideal) 0.00 6.00
library setup time -0.18 5.82
data required time 5.82
--------------------------------------------------------------------------
data required time 5.82
data arrival time -5.82
--------------------------------------------------------------------------
slack (MET) 0.00
*******************Power************************
Cell Internal Power = 2.5293 W (68%)
Net Switching Power = 1.1864 W (32%)
Cell Leakage Power = 42.3871 uW
---------
Total Dynamic Power = 3.7157 W (100%)
************************************************
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