Topic: ethereum mining with fpga (Read 1177 times)
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FPGA Cards and FPGA Mining Rig NR104 https://nocroom.com/fpga/
Hi Hakan
Thank you for contacting me regarding the VCU1525 board. The manufacturer of this board, Xilinx, is keeping tight control of ordering for now due to the constrained supply of this product. The delivery is running between 3 and 4 weeks right now for the -P version and 7-8 weeks for the -A version. Once an order is placed we can try to expedite it with the factory.
Each board has been tested for Ethereum and has achieved 9.375MH/s rate, so to replicate and exceed your current GPU performance you would need 4 boards.
The orderable part numbers are DK-U1-VCU1525-A-G for the actively cooled version (comes with fan) and DK-U1-VCU1525-P-G for the passively cooled version, and the price for 1 to 24 units is $4,995.00USD each shipping from the US.
These boards come with a 90 day warranty. Orders are non-cancelable, non-returnable.
I have also attached a statement of assurance form that we need filled out and signed to set you up in our system.
Thanks
Jason Harvey
[email protected]om
***************************************
mail thrown at me
Thank you for contacting me regarding the VCU1525 board. The manufacturer of this board, Xilinx, is keeping tight control of ordering for now due to the constrained supply of this product. The delivery is running between 3 and 4 weeks right now for the -P version and 7-8 weeks for the -A version. Once an order is placed we can try to expedite it with the factory.
Each board has been tested for Ethereum and has achieved 9.375MH/s rate, so to replicate and exceed your current GPU performance you would need 4 boards.
The orderable part numbers are DK-U1-VCU1525-A-G for the actively cooled version (comes with fan) and DK-U1-VCU1525-P-G for the passively cooled version, and the price for 1 to 24 units is $4,995.00USD each shipping from the US.
These boards come with a 90 day warranty. Orders are non-cancelable, non-returnable.
I have also attached a statement of assurance form that we need filled out and signed to set you up in our system.
Thanks
Jason Harvey
[email protected]om
***************************************
mail thrown at me
Has anyone heard of FPGA Eth/Zec/XMr M3 miner, the BuriedOne has just published a video...
3.6 Ghs 800w???
3.6 Ghs 800w???
hi every one
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
Hi this board maybe interesting for you https://www.bittware.com/fpga/xilinx/boards/xupvv4/#datasheet
It doesn't contain the GDDR5, but contain DDR4 and it has ultraBRAM
So you can solve memory problems designing the new board with like this chips to solve the memory bandwidth problem
https://www.xilinx.com/support/documentation/white_papers/wp485-hbm.pdf
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01264-stratix10mx-devices-solve-memory-bandwidth-challenge.pdf
I'm also interested in design IP core for ethash, analyzing the architecture of ethereum, haven't found yet any problem why it can't be implemented in FPGA SoC
What makes you think a 2GB DAG size is a reasonable design goal? Check out the info at: https://investoon.com/tools/dag_size
I presume you want your design to have a chance to ROI within a year?
How would your design be a better choice than any ol' 1081ti GPU?
I presume you want your design to have a chance to ROI within a year?
How would your design be a better choice than any ol' 1081ti GPU?
I mean that with using FPGA's we can increase the size of RAM as DAG file size gets larger . in this way we do not have to spend extra money for 1080ti with 11 GB memory that even 50% of its memory size will be useless till 2024.
I don't say that I want to get the hash power of a 1080ti by a single FPGA, but I'm looking to find that will it be a better ROI with FPGA's or not?
What makes you think a 2GB DAG size is a reasonable design goal? Check out the info at: https://investoon.com/tools/dag_size
I presume you want your design to have a chance to ROI within a year?
How would your design be a better choice than any ol' 1081ti GPU?
I presume you want your design to have a chance to ROI within a year?
How would your design be a better choice than any ol' 1081ti GPU?
I think a fpga simulating a memorycontroller can help. But I don´t know to handle GDDR5 RAM (with 2000 MHz) with a fpga 
But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
to not die ignorant what fpga´s is? But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
I know what a fpga is. I made something with fpga boads including RAM, one year before. The bandwith to the RAM was very low.
The normal way to control the RAM is the slow SPI interface, so i think it is the bottle neck and must be replaced, if you want high bandwith.
But anyway, i wish you success !
As we know we are not getting the whole DAG file at the beginning also because of the FPGA's limited bandwidth (~0.8 GB/s ) there's no need to high-speed RAMs cause even the DDR2 RAM's have 1.2 GB/s bandwidth, and it will be enough for our project. We are just looking to see if its possible that several FPGA's use one main RAM for DAG file.
I think a fpga simulating a memorycontroller can help. But I don´t know to handle GDDR5 RAM (with 2000 MHz) with a fpga
But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
to not die ignorant what fpga´s is? But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
I know what a fpga is. I made something with fpga boads including RAM, one year before. The bandwith to the RAM was very low.
The normal way to control the RAM is the slow SPI interface, so i think it is the bottle neck and must be replaced, if you want high bandwith.
But anyway, i wish you success !
Much smarter people than us all (no offense, really) have tried to create an ASIC for ethash and other ASIC-resistant algorithms and have failed to provide a reasonable solution besides a bunch of GPUs on a custom PCB, possibly in MXM form factor.
I think a fpga simulating a memorycontroller can help. But I don´t know to handle GDDR5 RAM (with 2000 MHz) with a fpga
But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
to not die ignorant what fpga´s is? But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
I think a fpga simulating a memorycontroller can help. But I don´t know to handle GDDR5 RAM (with 2000 MHz) with a fpga
But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
But a modern grafic card has all you want (ok,no fpga´s, but CU´s) and is faster, cheaper and need less power compared to fpga´s.
hi every one
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
our team is looking to find a way to mine ethereum using a FPGA or another suitable Alternative way.
Ethash algorithm contains DAG file so it needs a memory (~ 2GB, that's a lot more than any FPGA's BRAM), by the way increasing the difficulty made mining harder so we need more bandwidth than a regular FPGA chip, in this case, we are trying to know that is there any way for FPGA to have a parallel processing to achieve more bandwidth and hash rate ?
to solve the memory problem we need to use RAM for fpga's but is there any way to have parallel processing (several fpgas) with just one main RAM to decrease the cost ?
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