Topic: FPGA Mining and porting (Read 700 times)
I reposted this in the FPGA section. You should get some replies now!
I'm a software engineer with electronics as one of my big hobbies and though specifically FPGAs.
My own result this far is a initial understanding of BitCoins and mining and a port of the Verilog_Xilinx source code to suit my own board. I use a Digilent Microblaze Starter Kit which includes a Spartan-3E 1600E. Up to this point this FPGA seemed to be able to host almost anything I threw at it, but after finding the wonderful world of FPGA Bitcoin Mining this FPGA shows its limitations.. After I ported the code and built it in ISE 14.1, attached a heat sink to the FPGA, tweeked some settings in ISE, did some simple Floor-planning, I've managed the following:
I managed to cram in a "LOOP_LOG2=3"-circuit (which should be the same as 32 parallel computing units) which can run at 60 Mhz (somewhat overclocked) taking 85% of the circuit this far. With a theoretical max hash of about 15 MH/s now, it is not a speed monster..
By unrolling the loop with "LOOP_LOG2=3" I come to the conclusion that this should be the same as: MH/s = MainFreq/4. Is this correct? If so, the above circuit should average about 15MH/s. When letting it run for a while I get much lower values, about 8-10MH/s. Anybody got an idea why? Current-limitation on this standard board? Even though it can be hard to see, lower frequencies (and less loop-unrolling) seem to comply to the above rule to calculate throughput.
I'm planning to release the port in GIT, but maybe no one would have use of it, since my Starter Kit is getting old..
Anyone tried to pipeline this core? I've read a paper about it and they mentioned that due to the feedback-nature of the circuit only quasi-pipelining is possible. Anyone care to comment? Are there open-source FPGA implementations using this syntax? Are there known closed-source implementations using this? What's the gain?
Another question, is there any FPGA-based Miner that actually handles the Ethernet-connection itself? Open-source?
Is there any implementation that makes it possible to connect VGA-monitor for better insight into the FPGA-miner? Maybe I should give it a go.. what numbers would one like to have?
My own result this far is a initial understanding of BitCoins and mining and a port of the Verilog_Xilinx source code to suit my own board. I use a Digilent Microblaze Starter Kit which includes a Spartan-3E 1600E. Up to this point this FPGA seemed to be able to host almost anything I threw at it, but after finding the wonderful world of FPGA Bitcoin Mining this FPGA shows its limitations.. After I ported the code and built it in ISE 14.1, attached a heat sink to the FPGA, tweeked some settings in ISE, did some simple Floor-planning, I've managed the following:
I managed to cram in a "LOOP_LOG2=3"-circuit (which should be the same as 32 parallel computing units) which can run at 60 Mhz (somewhat overclocked) taking 85% of the circuit this far. With a theoretical max hash of about 15 MH/s now, it is not a speed monster..
By unrolling the loop with "LOOP_LOG2=3" I come to the conclusion that this should be the same as: MH/s = MainFreq/4. Is this correct? If so, the above circuit should average about 15MH/s. When letting it run for a while I get much lower values, about 8-10MH/s. Anybody got an idea why? Current-limitation on this standard board? Even though it can be hard to see, lower frequencies (and less loop-unrolling) seem to comply to the above rule to calculate throughput.
I'm planning to release the port in GIT, but maybe no one would have use of it, since my Starter Kit is getting old..
Anyone tried to pipeline this core? I've read a paper about it and they mentioned that due to the feedback-nature of the circuit only quasi-pipelining is possible. Anyone care to comment? Are there open-source FPGA implementations using this syntax? Are there known closed-source implementations using this? What's the gain?
Another question, is there any FPGA-based Miner that actually handles the Ethernet-connection itself? Open-source?
Is there any implementation that makes it possible to connect VGA-monitor for better insight into the FPGA-miner? Maybe I should give it a go.. what numbers would one like to have?
Jump to: