Hi,
can either of you guys drop me this file or supply an upto-date link, I have a couple of the XUPV5 boards and would like to run some tests on improving the results.
HC
Topic: FPGA Mining, TheSeven (Read 1075 times)
Will do, thanks a lot!
Is there any chance you'd let me have your vhdl code and ucf file for it too? One of the reasons I was interested in getting it working was to practice my VHDL. I'd understand if you wanted to keep that to yourself however. There's also a board with a Virtex-6 LX760 lying around that I might be able to test it on, not sure if anyone's tried that yet.
Sure! http://dl.dropbox.com/u/23683845/xupv5lx110t-simplers232miner-120mhz-131stage-cleaned.7z
Feel free to play with that, just let me know if you successfully manage to run that thing at more than 120MH/s
Many many thanks for that. It didn't take me long to get working. The import for worker.theseven.simplers232 needed adding to my config.py.
I'll send a few bitcoins your way for your help (not sure what's a reasonable rate, 1?) and keep the other pools active too, although I won't be mining constantly.
Is there any chance you'd let me have your vhdl code and ucf file for it too? One of the reasons I was interested in getting it working was to practice my VHDL. I'd understand if you wanted to keep that to yourself however. There's also a board with a Virtex-6 LX760 lying around that I might be able to test it on, not sure if anyone's tried that yet.
Thanks again.
I'll send a few bitcoins your way for your help (not sure what's a reasonable rate, 1?) and keep the other pools active too, although I won't be mining constantly.
Is there any chance you'd let me have your vhdl code and ucf file for it too? One of the reasons I was interested in getting it working was to practice my VHDL. I'd understand if you wanted to keep that to yourself however. There's also a board with a Virtex-6 LX760 lying around that I might be able to test it on, not sure if anyone's tried that yet.
Thanks again.
I'm using a 100MHz input clock, and it took quite a lot of tries until that thing managed to synthesize the full hashing core at 120MHz.
So unless you want to spend several weeks fighting with ISE, just use my bitstream: http://dl.dropbox.com/u/23683845/xupv5lx110t-simplers232miner-120mhz.bit
That one should work with MPBM's SimpleRS232 module out of the box.
So unless you want to spend several weeks fighting with ISE, just use my bitstream: http://dl.dropbox.com/u/23683845/xupv5lx110t-simplers232miner-120mhz.bit
That one should work with MPBM's SimpleRS232 module out of the box.
Hi
I realise this is probably unlikely to happen, but I've joined as I'd really like some advice from TheSeven if they have the time. I have the same XUPV5 -LZ110T FPGA board as you (I think, judging by a picture I saw) and I'm trying to get the VHDL miner to work.
Firstly, I could only get it to synthesize when I reduced the depth, it was 6, I now have it at 2, it might work higher but I haven't tested it yet, is this to be expected? Also, what should I connect the clk_in port to? I had to it connected to CLK_33MHZ_FPGA (AH17) but got errors from the python program saying that it timed out waiting for a response. I then read the post about adjusting the UART clock divider, which I attempted to do based on the formulas you posted, but then got the "got bad message from fpga: 28" error.
Basically, am I connecting the right pin to clk_in? I'm just trying it with CLK_27MHZ_FPGA now. Is there anything else I should be changing, such as CLKIN_PERIOD in top.vhd? I have tried changing it to 30ns (i.e. 1/33MHz-ish) with no joy.
Hopefully you'll read this, or someone else might help.
Thanks for reading..
I realise this is probably unlikely to happen, but I've joined as I'd really like some advice from TheSeven if they have the time. I have the same XUPV5 -LZ110T FPGA board as you (I think, judging by a picture I saw) and I'm trying to get the VHDL miner to work.
Firstly, I could only get it to synthesize when I reduced the depth, it was 6, I now have it at 2, it might work higher but I haven't tested it yet, is this to be expected? Also, what should I connect the clk_in port to? I had to it connected to CLK_33MHZ_FPGA (AH17) but got errors from the python program saying that it timed out waiting for a response. I then read the post about adjusting the UART clock divider, which I attempted to do based on the formulas you posted, but then got the "got bad message from fpga: 28" error.
Basically, am I connecting the right pin to clk_in? I'm just trying it with CLK_27MHZ_FPGA now. Is there anything else I should be changing, such as CLKIN_PERIOD in top.vhd? I have tried changing it to 30ns (i.e. 1/33MHz-ish) with no joy.
Hopefully you'll read this, or someone else might help.
Thanks for reading..
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