Designing for a specific FPGA and using its timing quirks to your advantage goes against all the basics I hear -- that FPGAs are meant for quick prototyping. This is a good sign of the old hacker spirit.
I've also wondered how much FPGA circuit designs are limited by programmers who are used to sequential designs. For example, could you design a clockless network that spits out the result of SHA256. I dabble in analog electronics, where you can do fairly complicated things without any clocking, so I like to imagine how far you could extend these ideas in the digital realm. Then again, I understand it's the analog properties of a circuit that introduce delay, and one way to deal with that delay is clocking.
Anyway, good luck with the project
I do hope you would opensource it at some point, so we can all learn something after you've earned enough coin. 
