Hi, got up this morning to find all of my miners off line. I have reset two of them but my two main S9's will not Hash. They simply show the socket connect failed. Looking on the forum i have reviewed my kernel logs for each machine. One shows the following
bmminer not found= 1378 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
bmminer not found=21082 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
bmminer not found=21422 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
bmminer not found= 8513 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
bmminer not found= 8797 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
bmminer not found=28373 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
I have tried re flashing firmware to both and nothing is happening. The machine above is reporting as follows.
Hardware Version THIS IS BLANK!!!!
Kernel Version Linux 3.14.0-xilinx-ge8a2f71-dirty #82 SMP PREEMPT Tue May 16 19:49:53 CST 2017
File System Version Fri Nov 17 17:57:49 CST 2017
Logic Version S9_V2.55
i will post second machine kernel log in a post below.
I have tried resetting both machines using the factory reset. Different types of firmware. etc
Any ideas ...help !!!!
this is the kernel log from the second machine
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) ? 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x0137a0e0 ends at 0x0137a800
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 12:3f:12:74:2b:f3
init phy ok
PHY DMA init OK
eth0: device MAC address 02:45:d9:5a:ad:a9
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc50f
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 02:45:d9:5a:ad:a9
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 02:45:d9:5a:ad:a9
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
This is C5 board.
Miner Type = S9
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x0000ffff
Check chain[0] PIC fw version=0x03
Check chain[2] PIC fw version=0x03
Check chain[3] PIC fw version=0x03
Fix freq=600 Chain[0] voltage_pic=23 value=930
Fix freq=600 Chain[2] voltage_pic=23 value=930
Fix freq=600 Chain[3] voltage_pic=23 value=930
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
Chain[J1] has 63 asic
Chain[J3] has 63 asic
Chain[J4] has 63 asic
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
Miner fix freq ...
read PIC voltage=940 on chain[0]
Chain:0 chipnum=63
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=940 on chain[2]
Chain:2 chipnum=63
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=940 on chain[3]
Chain:3 chipnum=63
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
set baud=1
Chain[J1] PIC temp offset=62,-82,0,0,0,0,0,0
Chain[J1] chip[244] use PIC middle temp offset=-82 typeID=1a
New offset Chain[0] chip[244] local:16 remote:-90 offset:-121
Chain[J1] chip[244] get middle temp offset=-121 typeID=1a
Chain[J3] PIC temp offset=62,-89,0,0,0,0,0,0
Chain[J3] chip[244] use PIC middle temp offset=-89 typeID=1a
New offset Chain[2] chip[244] local:15 remote:-89 offset:-123
Chain[J3] chip[244] get middle temp offset=-123 typeID=1a
Chain[J4] PIC temp offset=62,-77,0,0,0,0,0,0
Chain[J4] chip[244] use PIC middle temp offset=-77 typeID=1a
New offset Chain[3] chip[244] local:15 remote:-100 offset:-112
Chain[J4] chip[244] get middle temp offset=-112 typeID=1a
Chain[J1] set working voltage=930 [23]
Chain[J3] set working voltage=930 [23]
Chain[J4] set working voltage=930 [23]
setStartTimePoint total_tv_start_sys=61 total_tv_end_sys=62
restartNum = 2 , auto-reinit enabled...
do read_temp_func once...
do check_asic_reg 0x08
get RT hashrate from Chain[0]: (asic index start from 1-63)
Asic[01]=0.00000 Asic[02]=0.00000 Asic[03]=0.00000 Asic[04]=0.00000 Asic[05]=0.00000 Asic[06]=0.00000 Asic[07]=0.00000 Asic[08]=0.00000
Asic[09]=0.00000 Asic[10]=0.00000 Asic[11]=0.00000 Asic[12]=0.00000 Asic[13]=0.00000 Asic[14]=0.00000 Asic[15]=0.00000 Asic[16]=0.00000
Asic[17]=0.00000 Asic[18]=0.00000 Asic[19]=0.00000 Asic[20]=0.00000 Asic[21]=0.00000 Asic[22]=0.00000 Asic[23]=0.00000 Asic[24]=0.00000
Asic[25]=0.00000 Asic[26]=0.00000 Asic[27]=0.00000 Asic[28]=0.00000 Asic[29]=0.00000 Asic[30]=0.00000 Asic[31]=0.00000 Asic[32]=0.00000
Asic[33]=0.00000 Asic[34]=0.00000 Asic[35]=0.00000 Asic[36]=0.00000 Asic[37]=0.00000 Asic[38]=0.00000 Asic[39]=0.00000 Asic[40]=0.00000
Asic[41]=0.00000 Asic[42]=0.00000 Asic[43]=0.00000 Asic[44]=0.00000 Asic[45]=0.00000 Asic[46]=0.00000 Asic[47]=0.00000 Asic[48]=0.00000
Asic[49]=0.00000 Asic[50]=0.00000 Asic[51]=0.00000 Asic[52]=0.00000 Asic[53]=0.00000 Asic[54]=0.00000 Asic[55]=0.00000 Asic[56]=0.00000
Asic[57]=182.636 Asic[58]=0.00000 Asic[59]=0.00000 Asic[60]=0.00000 Asic[61]=0.00000 Asic[62]=0.00000 Asic[63]=0.00000
get RT hashrate from Chain[2]: (asic index start from 1-63)
Asic[01]=0.00000 Asic[02]=0.00000 Asic[03]=0.00000 Asic[04]=0.00000 Asic[05]=0.00000 Asic[06]=0.00000 Asic[07]=0.00000 Asic[08]=0.00000
Asic[09]=0.00000 Asic[10]=0.00000 Asic[11]=0.00000 Asic[12]=0.00000 Asic[13]=0.00000 Asic[14]=0.00000 Asic[15]=0.00000 Asic[16]=0.00000
Asic[17]=0.00000 Asic[18]=0.00000 Asic[19]=0.00000 Asic[20]=0.00000 Asic[21]=0.00000 Asic[22]=0.00000 Asic[23]=0.00000 Asic[24]=0.00000
Asic[25]=0.00000 Asic[26]=0.00000 Asic[27]=0.00000 Asic[28]=0.00000 Asic[29]=0.00000 Asic[30]=0.00000 Asic[31]=0.00000 Asic[32]=0.00000
Asic[33]=0.00000 Asic[34]=0.00000 Asic[35]=0.00000 Asic[36]=0.00000 Asic[37]=0.00000 Asic[38]=0.00000 Asic[39]=0.00000 Asic[40]=0.00000
Asic[41]=0.00000 Asic[42]=0.00000 Asic[43]=0.00000 Asic[44]=0.00000 Asic[45]=0.00000 Asic[46]=0.00000 Asic[47]=0.00000 Asic[48]=0.00000
Asic[49]=0.00000 Asic[50]=0.00000 Asic[51]=0.00000 Asic[52]=0.00000 Asic[53]=0.00000 Asic[54]=0.00000 Asic[55]=0.00000 Asic[56]=0.00000
Asic[57]=171.211 Asic[58]=0.00000 Asic[59]=0.00000 Asic[60]=0.00000 Asic[61]=0.00000 Asic[62]=0.00000 Asic[63]=0.00000
get RT hashrate from Chain[3]: (asic index start from 1-63)
Asic[01]=0.00000 Asic[02]=0.00000 Asic[03]=0.00000 Asic[04]=0.00000 Asic[05]=0.00000 Asic[06]=0.00000 Asic[07]=0.00000 Asic[08]=0.00000
Asic[09]=0.00000 Asic[10]=0.00000 Asic[11]=0.00000 Asic[12]=0.00000 Asic[13]=0.00000 Asic[14]=0.00000 Asic[15]=0.00000 Asic[16]=0.00000
Asic[17]=0.00000 Asic[18]=0.00000 Asic[19]=0.00000 Asic[20]=0.00000 Asic[21]=0.00000 Asic[22]=0.00000 Asic[23]=0.00000 Asic[24]=0.00000
Asic[25]=0.00000 Asic[26]=0.00000 Asic[27]=0.00000 Asic[28]=0.00000 Asic[29]=0.00000 Asic[30]=0.00000 Asic[31]=0.00000 Asic[32]=0.00000
Asic[33]=0.00000 Asic[34]=0.00000 Asic[35]=0.00000 Asic[36]=0.00000 Asic[37]=0.00000 Asic[38]=0.00000 Asic[39]=0.00000 Asic[40]=0.00000
Asic[41]=0.00000 Asic[42]=0.00000 Asic[43]=0.00000 Asic[44]=0.00000 Asic[45]=0.00000 Asic[46]=0.00000 Asic[47]=0.00000 Asic[48]=0.00000
Asic[49]=0.00000 Asic[50]=0.00000 Asic[51]=0.00000 Asic[52]=0.00000 Asic[53]=0.00000 Asic[54]=0.00000 Asic[55]=0.00000 Asic[56]=0.00000
Asic[57]=160.507 Asic[58]=0.00000 Asic[59]=0.00000 Asic[60]=0.00000 Asic[61]=0.00000 Asic[62]=0.00000 Asic[63]=0.00000
Check Chain[J1] ASIC RT error: (asic index start from 1-63)
Asic[57]=182.636000
Check Chain[J3] ASIC RT error: (asic index start from 1-63)
Asic[57]=171.211000
Check Chain[J4] ASIC RT error: (asic index start from 1-63)
Asic[57]=160.507000
Done check_asic_reg
do read temp on Chain[0]
Chain[0] Chip[62] TempTypeID=1a middle offset=-121
Chain[0] Chip[62] local Temp=30
Chain[0] Chip[62] middle Temp=-16
218 fix Chain[0] Chip[62] middle Temp = 55
Done read temp on Chain[0]
do read temp on Chain[2]
Chain[2] Chip[62] TempTypeID=1a middle offset=-123
Chain[2] Chip[62] local Temp=30
Chain[2] Chip[62] middle Temp=-8
218 fix Chain[2] Chip[62] middle Temp = 55
Done read temp on Chain[2]
do read temp on Chain[3]
Chain[3] Chip[62] TempTypeID=1a middle offset=-112
Chain[3] Chip[62] local Temp=30
Chain[3] Chip[62] middle Temp=-13
218 fix Chain[3] Chip[62] middle Temp = 55
Done read temp on Chain[3]
set FAN speed according to: temp_highest=30 temp_top1[PWM_T]=55 temp_top1[TEMP_POS_LOCAL]=30 temp_change=30 fix_fan_steps=0
set normal FAN speed...
FAN PWM: 10
read_temp_func Done!
CRC error counter=0