Topic: How many gates BFL and Avalon used for each core? (Read 1741 times)
21,000,000 max.
I think reasonable estimate could be made by finding out the size of chip and then finding some chip with know gate density or gate count made with similar technology.
And I don't have idea of either one
And I don't have idea of either one
The size of chip that Max wants to gate is 20nm for this fall/winter delivery.
@ ShadesOfMarble
9,000 ? do you have reference ?
9,000 ? do you have reference ?
You're new to this Internet thing, aren't you?
http://lmgtfy.com/?q=9000&l=1
I think reasonable estimate could be made by finding out the size of chip and then finding some chip with know gate density or gate count made with similar technology.
And I don't have idea of either one
And I don't have idea of either one
@Gomeler
If you knew about ASIC design you wouldn't have made the comment #3, thanks for the first 2. So please don't troll. And I asked the question because they may have talked about it publicly that I didn't came across yet.
If you knew about ASIC design you wouldn't have made the comment #3, thanks for the first 2. So please don't troll. And I asked the question because they may have talked about it publicly that I didn't came across yet.
I will agree that I do not posses the skill set to develop an ASIC. Given past experiences with VHDL I suspect I could at least create a design that that implements BTC's hashing algorithm but I would have no clue how to make the jump from a wad of code to a hardware implementation of my design. From what I understand, a fully unrolled core is simpler to design so I'd go with that to start. At the end of the day I could give you a gate count for my implementation but I imagine someone like ngzhang would know more tricks to optimize the design by removing redundant components and increase the maximum frequency of the design. At the end of the day that's why he works and builds hardware while I tinker with higher level languages.
I do not troll. If I trolled I'd have given you numbers that sounded believable but were full of crap
@Gomeler
If you knew about ASIC design you wouldn't have made the comment #3, thanks for the first 2. So please don't troll. And I asked the question because they may have talked about it publicly that I didn't came across yet.
If you knew about ASIC design you wouldn't have made the comment #3, thanks for the first 2. So please don't troll. And I asked the question because they may have talked about it publicly that I didn't came across yet.
You are likely to get not answer due to 1) nobody outside of those companies know the answer 2) those companies aren't likely going to reveal that answer 3) you come off as foolish and uneducated. Regardless of what financial resources you have, you appear to be using this forum in an attempt to understand how one goes about building an ASIC that hashes. This does not bode well for your endeavor, if it is anything more than a scam. Perhaps instead you should configure a FPGA to understand the process and then proceed from there? There are a few FPGA designs scattered across the web to help you get started.
Avalon used 42.
BFL uses zero.
The BFL miners have infinite performance, they have mined millions of USD worth of payments while using zero electricity.
Avalon's performance is a bit less impressive but a bit more tangible.
BFL uses zero.
The BFL miners have infinite performance, they have mined millions of USD worth of payments while using zero electricity.
Avalon's performance is a bit less impressive but a bit more tangible.
awesome troll thread.
watching!
watching!
Crowd sourced engineering sounds like a recipe for disaster.
In no way am I doing crowd sourced engineering, I am just checking some things.
@ ShadesOfMarble
9,000 ? do you have reference ?
Not 9000, over 9000.
Source: Vegeta
Crowd sourced engineering sounds like a recipe for disaster.
In no way am I doing crowd sourced engineering, I am just checking some things.
@ ShadesOfMarble
9,000 ? do you have reference ?
42
42 ? were they golden gates or pearly gates? 
come on I am not stupid
42 is the answer to everything..
+1 definitely 42
42
42 ? were they golden gates or pearly gates? come on I am not stupid
42 is the answer to everything..
I think it's more like over 9000.
Crowd sourced engineering sounds like a recipe for disaster.
This is not just an Internet forum, here are a lot of smart people. There are many SHA core implementations and Avalon said that they looked into buying SHA core IP but theirs was better so they decided not to. There aren't any engineers that specialize (made more than one) in ASIC design for bitcoin, it's too new. No one knows everything and I am just crowd sourcing knowledge to make sure that I make most efficient and high performance product. That is why I am rechecking some engineering against the crowd.
How many gates BFL and Avalon used for each core?
Thanks
Thanks
Why do you keep asking these simple design oriented guestions if you claim to have very potent engineers working on designing an ASIC for you? These questions are not something a credible company needs to ask from a internet forum.
42
42 ? were they golden gates or pearly gates? come on I am not stupid
42
How many gates BFL and Avalon used for each core?
Thanks
Thanks
Jump to: