Topic: How much would it actually cost to design an ASIC? (Read 1987 times)

Many many costs.  Design, employee costs, software costs for things like cadence or other logic software.  Usually it's 3 to 4+ companies.   Company A asks company B like easic, esilicon, etc to make an ASIC design for mining bitcoins.  Company B asks a foundry like global foundries or tsmc to make a set or the chips in a specific volume.    Then the foundry either fulfills a order or goes to another company D for a high volume order.  Company C or D could charge 1 cent to 4 cents a chip in high volume, 100s of thousands.

Okay that's inline with what I was expecting for this older tech. Just out of curiosity, what are the actual cost items, aside from salary? Is that just the fee charged by the companies that do tape outs? The costs charged by the fab to do a mask?

I find the whole thing quite fascinating.

Having some inside knowledge of NRE for development of at least "from scratch" 130nm ASIC from planning -> First tape out I ballpark the costs to between $100-$300.000 depending on whether or not the developers are paid salary for their efforts or are willing to accept ownership in project as payment/treat the development as a hobby project.

The accelerated costs involved in 65nm or higher density are mostly referee able to the vastly increased costs for tape out, production etc. as foundries for bleeding edge density charge far more and have much tighter cycles and less production capabilities for these higher density chips. There are also far more foundries that can take on 180-130nm production.

Depends on usages. If you ask low performance, then the price can be very low. I only notice one thing. Smaller the more , higher performance, more expensive.

1000K USD is just minimal for GPU like design, including mould making.

Just out of curiosity, what is it that makes larger feature size chips cheaper to design? Is it just related to unintended capacitance and things like that?


I suppose I could do the Verilog myself, I'm just concerned about how much time it would take me vs. a professional. But this is pretty speculative anyway.


Hmm, that's inline with the prices I heard earlier, which included lower costs for 110/130nm designs (in the 10s of thousands).  You didn't happen to ask what it would cost at those sizes, did you?

Costs 100's of thousands just for the NRE not including the tape out, mask and wafer you are looking at a million or more if so easy everyone would be producing their own asic chips.

It depends on many factors:
- Technology node - older ones, like the ones you mention, are less expensive even at the design stage.
- do you plan on writing the Verilog code yourself or just print out a copy of the SHA-256 standard and tell them to implement a Bitcoin miner?
- if you go to a tier 1 design house, say, the design house division of Synopsys, it will be more expensive than if you go to, say, a small fly-by-night vendor operating out of a garage and using cracked design tools which they stole from their local university

But to give you a rough idea, when I gave my own Verilog code to a second-tier design house and asked for a quote for the physical design at the 65 nm technology node, the quote was $150K.

I've seen numbers like a few tens of thousands of dollars for an initial tapeout on lower-end processes (like 110, 130 or 180nm), at least if you know what you're doing. How realistic is that outside of China?

Basically what I'm wondering is: How much would the up-front R&D cost for various feature sizes? Beyond that - my impression is that it's easier to get chips fabricated at larger sizes as well (less competition for limited fab slots). 

There are companies like Uniquify (doing HashFast) and ORsoC (doing KnC) but I would imagine their services are pretty expensive, are there cheaper companies with a proven track record that could handle a 110nm design without much cost, and on a relatively short time-frame?

I realize that 110nm+ is kind of obsolete at this point, but my idea would be to design the chip and then simply charge a license fee. So, you could have multiple companies competing to sell these chips at low a cost as possible, or people could even do group buys directly from the fab, choosing whatever kind of packaging they want.

(I'm not an ASIC designer - if that's not obvious at this point, although I did take a class on digital circuit design in college, which used FPGAs. I have some ideas that I think are interesting that could boost performance and make the chips much easier for DIYers as well)