No. You going to disagree with what I said or just generally disagree.
Low yield rate has nothing to do with the difficulty to "design for". You design for a fully functional chip, and in the event that a chip bins less than A grade, it's not an issue.
High BGA count really doesn't mean anything. You either construct the component on your own, or use a pre-existing model. This process is only time intensive and really does not reflect on "difficult to design for". Otherwise, the bulk of the BGA pads are for Vdd/Vcc and ground, all of which are just tied to their respective plane(s). The few IO pins that do exist can be adequately routed through a multi-layer PCB.
Multiphase DC/DC regulation isn't rocket science. In fact, most MP controller documentation makes recommendations as to what MOSFETs are ideal as well as the desired pad configuration. Further, KnC didn't even use their own implementation of a multiphase design. They used complete design solutions from GE and Ericsson.
I agree that there are some challenges in designing a PCB for these chips, but the design challenges don't have much to do with what you've stated, if at all.
