I am assumming you mean 5.7 cents per kWh because watts is a measure of power and electricity is paid per unit of energy.
watt = power KW = power
watt hours = energy kWh = energy
If you pay 5.7 cents per kWh then FPGA are a non-issue (at least in the near term).
The true metric is total cost of ownership over expected lifespan. So capital cost + all energy cost / # of hashes produced in say 18 months or 3 years. With very low power rates you can keep a low TCO without FPGAs.
TL/DR version is all that matter is the total cost (equpment + electricity + repairs + labor/management) to produce 1 PH (1 quadrillion hashes) over the lifetime (either actual or economic) over the equipment (or life of under warranty replacements.
To answer your direction question (some ballpark figures):
Thats the info I needed. Thanks! watt = power KW = power
watt hours = energy kWh = energy
If you pay 5.7 cents per kWh then FPGA are a non-issue (at least in the near term).
The true metric is total cost of ownership over expected lifespan. So capital cost + all energy cost / # of hashes produced in say 18 months or 3 years. With very low power rates you can keep a low TCO without FPGAs.
TL/DR version is all that matter is the total cost (equpment + electricity + repairs + labor/management) to produce 1 PH (1 quadrillion hashes) over the lifetime (either actual or economic) over the equipment (or life of under warranty replacements.
To answer your direction question (some ballpark figures):
Code:
CPU mining: .01 to 0.25 MH/W (totally uncompetitive at this point)
Unoptimized non-dedicated GPU rig: <2 MH/W (gaming computer w/ 1 or 2 GPUs that someone used for mining)
Optimized GPU rig: 2MH/W to 3 MH/W (requires good planning and part selection)
Underclocked & Undervolted rig: 4MH/W to 5 MH/W (requires good planning and part selection)
BFL Single: ~9 MH/W (unknown chp, my guess is it is a "last gen" 60nm FPGA)
ztex, 6500, Icarus boards: ~20 MH/W (all based on 45nm Spartan-6 FPGA)
RigBox: ~20 MH/w (untested specs, unknown chip)
Artix-7 based board: ~30MH/W to 40 MH/W (estimate based on theoretical improvement from 45nm to 32nm FPGA)
LargeCoin: ~200 MH/W (sASIC design, untested spec)
Full Custom ASIC: ~500 MH/W+ (theoretical estimate based on SHA-2 "testbed" processor)
Think of it more as the upper limit of what is possible with current silicon. I took the wattage and speed of the SHA "testbed" chip which was used for testing the various algorithms used in one of which eventually became SHA-256 and quadrupled it to account for 2 die shrinks ("testbed" processor was @ 130nm). A 45nm custom ASIC (chip that does nothing but SHA-256 hashing) should be in the ballpark of 500 MH/s.