Topic: Nanominer Announcement (Read 11700 times)

I agree. I was really pushing it running at that speed (it was a bit of a dare to see if I could match Makomk's results), and you have to be very careful with the power and cooling (it certainly won't work just using the USB supply, and would be foolish to try).

I'm not really that much of an expert with the Quartus software, so by tweaking the compiler settings it may be possible to better this (the fmax for this 170MHz build was around 150MHz, so it should not really have worked at all). One thing to check is the PLL multiply/divide ratios as its using 50MHz * 17 / 5 which may not be an optimal way to configure it. I did try running at 180Mhz but got no hashes at all, and decided that was probably the best I could manage so I called it a day at that.

EDIT I just realized this is a year old thread, and only peripherally to do with the DE0-Nano. Perhaps Ersch would like to PM wondermine to see if he actually tested it at 40MH/s (he seems to still be active on the board, just about).

From the reame file:

40 MHash/s is  probably not possible, the 28.3 should be  possible, another design by makomk  is/was  running at 27,5 MHz, mayby you could push  it  a little further using the timing headroom of the chips and/or higher  volages and cooling  effort.

I had a second look. I think I was right in the first place. There are 76 'static' bytes in the header before the nonce. The midstate is the internal state of the hash core after hashing the first 64 bytes. The remaining 12 bytes will be paired up with the 4 byte nonce and 48 bytes of padding (The header is 80 bytes, but will be padded up to even multiple of 64 bytes - the sha256 blocksize).

So you really do need both the 32 byte midstate and the 12 byte 'data'.

But as you said; that's all in the control logic and I understand it's under development
Nice work!

I just took a quick look over Nanominer's code to see what he's doing.  He appears to be implementing SHA-256 a bit differently from the other approaches I've seen.  In particular, he has not unrolled the hash so it requires 64 clock cycles to complete each hash.  This would be analagous to compiling fpgaminer's code with LOG_LOOP2=6.  However, Nanominer then appears to be running 10 (configurable) of these cores in parallel with each other.  With a clock rate of 200MHz, this would lead to 200*10/(64*2) or about 16 MH/s by my calculations (since bitcoin hashes require two SHA-256 hashes each).

Wondermine, I'm not sure how you are coming up with the higher numbers for hash rates.  You would need to fit 50 of these on a 115K LE Cyclone IV along with the associated control circuitry in order to reach the same ballpark as can be achieved with fpgaminer's code with Makomk's modifications.  Do you really expect to be able to fit significantly more than this on this FPGA?

Oh, and if you want to preserve logic so that the optimizer does not get rid of it, use the preserve_fanout_free_node option in the assignments editor on the pin(s) you want to preserve and then you should be able to see how much additional optimization the compiler is capable of.

The "control" entity is obviously not meant to be the top of the design. You would accompany it with some kind of interface. Check the Open source miner project. There you have both RS232 interface and through Altera's "virtual wire".
As for bandwidth, you really don't need any. You just send a bunch of bytes (256-isch) to fire off a decent sized job

Well, maybe you could tell me  how you would call it to produce an ip core with 288 IOs for a device that has only 167 (or so) soldered on a board with some SDRAM etc ending with  80 Usable user IOs? Btw, you could enligten me wich microcontroller you plan to use that can write 256 bits at once. There is no bottleneck in using  some sort of serialization at all. And even if there were, you could always reduce the bandwith requirement by implementing roll-n-times in hardware.

Probably belongs in a SHA-256 thread, but I think what you're referring to has to do with precalculated(or -able) round values, and the initial value for those.
If there's a problem with the core.vhd, well, that's cause it's a work in progress, it'll get worked out.  And smaller...

Sorry to do the double-post but here are some numbers from the Cyclone V series FPGAs:

5CGXBC7D6F31C7 (Grade 7): 215.84 219.93 MHz

I'm liking this device family already.  As always, more to come.

P.S. This design does not "take up too many IOs", taking up too many IOs assumes you don't use some sort of serialization, which is rather absurd.

P.P.S. When compiled for the Stratix III EP3SL100F1152C2, the fmax is reported as 229.52 MHz, if you were wondering.

*These values are sans optimizations... if anyone can tell me how to make Quartus not synthesize away multiple cores, please let me know, and then I can give you some numbers that more likely reflect reality. (Although there's probably a problem with the core.vhd I need to fix... I work way too much and I have an exam later... I need to leave this alone.)

I'm still green when it comes to implementing these brute force cores, but I'm picking up.

I was browsing through your code and one thing struck me; you are using the 256 bit "data" input both for setting the internal state of the first sha round and as the end part of whats hashed in the first round.
In the Icarus and Open-Source-FPGA-Bitcoin-Miner code they have separate 256 bit init state and 96 bits of "data" that is appended to the nonce.

I can't quite work out what those 96 bits are. Bit 64 to 127 of the header. Reversed or not, it doesnt make much sense to me. It should at least not be the same as the init of the hash round.

Correction: the .zip file comes with only a quickly thrown together sdc and no qpf, just vhdl.
-Edit-
I can admit a mistake, you're right, with zero register duplication, no optimization, no resource sharing, etc, the core takes up 1925.  But let me be very clear: with optimizations that size goes down significantly, I've shut off all optimization in order to preserve logic that would otherwise be synthesized away.  To think that it won't use sharing with all of the XOR, AND, and + repetitions is absurd.
Apparently, however, I need to revamp my numbers, so I'll get something back to you on the core controller soon.
Also, in the design report the multiplexer restructure savings alone are 81 LEs, so 1925 -> 1844 for the current design.

In better news, I have my mining core shrunk from 768 -> 582 LEs as of today.


Does it port? Yes.  I don't have experience with the Stratix III series, does it use the same architecture (or similar) to that of the Stratix IV? If so the logic count would be decreased (compiling this on my Stratix IV gave me better numbers than the ones I've quoted).  I haven't looked into the pricing on that unit but work will continue and if Altera devices become advantageous, then we'll use them.

Good effort, Wondermine.

Hm, how did you get the number of  Logic cells without having a qpf and qsf file?
Why do you design a control logic  with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).

I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to  lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.

While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me . So you should recalculate your expectations with the number of 1925 LEs per hasher.

Interesting. Assuming your design can be ported from the Cyclone IV to the Stratix III, an EP3SL200 at 213MHz with 250 of your 800-LE cores would produce 416 Mhash/s. That would account exactly for the performance of the BitForce Single (rumored to be two EP3SL200 chips = 832 Mhash/s)...

I've got a preliminary Nanominer bitstream.  I'd like to be clear about whether it works: the digester is functional and has been tested with fpgaminer's code.  The rest of it looks fine in simulation, but the final product's *control circuitry* (i.e. state machines) may need fixing.  That said, the digester, which is the heart of it all *definitely works* at the size and performance I'm quoting here.  To prove this to everyone, I'm linking a .zip with the design files so you can see what I've been working on.  I only guarentee the digester (working_sha256.vhd) works 100% but so far the rest looks good.
Also that digester is sitting in for a better, more pipelined one that is smaller and performs better, but is still in the works.  I thought I'd let you all see something that actually can produce bitcoin.  The *current* specs are as follows:

Note:
-Compiled with Web Edition, I need to go to school and put this through the subscription one
-The fmax *varies* with the chip
-I do not know if this is analogous to Xilinx logic consumption; if it is, things are going well for all of us.
-The code is run preserving nodes with lost fanout because I don't have decent input and Quartus wants to synthesize away the duplicate cores (which are actually working in parallel
-I'm posting this for your interest, peace of mind, and maybe to whet your appetite, this is not to be scrutinized; it's a work in progress.  Constructive ideas, go for it, but picking the hell out of my design really won't do much good
-The new core is very promising, I expect a ~15% increase in performance in the next week

So:
Control Circuit Logic Consumption: 289 LC Registers (One per chip)
Core Logic Consumption: 1844 LC Registers (Iterative, as many as you like)
Cycles per Hash: 128
fmax @ Speed Grade 6: 201.73 MHz  (Cyclone IV)
Hashrate: 1.58MH/core
--edited to fix size--

So, it's not completely groundbreaking, yet, but there's a lot more where this came from.  This little announcement is more to say that I'm working, and this thing is coming.  I have my core less than 800 LEs (which would mean a DE0 hashrate of >40MH/s, and a significant improvement past 210MH/s on a Spartan-6), but I need to get timing logistics down, so more to come.

In the meantime, I'll post the VHDL for you all.  As always, donations are welcome, I do spend a hell of a lot of time on this and the way things are looking I'll break more records than just the DE0-Nano speed record.  I haven't broken the 210MH barrier yet, but soon enough, I just need to put a little more time into it.

Edit: By the way, it's not commented, and it's got an SDC but no QPF or anything, just straight VHDL.  All rights reserved me etc. cheers!

Can't wait to see news of a functioning prototype.  Love the expandable modular nature with additional boards.

Liking what I am seeing - wish there was MOAR hashes though... 

Quite so. But if you want fewer features at a higher price, Ztex is the way to go.

Nanominer seems like it's going to be a cheaper option than ztex is unless I'm looking at it wrong

Ztex?

Watching...

PS I'd rather have a "as-cheap-and-barebones-as-possible" FPGA.

No fancy screens or built in ethernet or cgminer. Just a bare FPGA board that I can connect with USB.

Yeah as long as it isn't a $25 part, I'd find it handy to have since I wouldn't be using a host system to run it.

I'd agree with you but it's not the best screen around, the cost is certainly negligible.  It's more so that someone using it as a standalone device can see what's going on with their miner without having to plug it in anywhere.

1 Mainboard, +4 Addons.
Expected power budget is 11W/board, but I'll try to cut down if possible.

Certainly seems competitive, at least compared to the current gen products available. What is the expected power budget, including the additional components?

So is it mainboard + 3 addons for a total of 4, or is it + 4 addons for a total of 5? If it is a total of 5, it would be 1Ghash for $1425 + shipping.

How does $325 USD + shipping sound for the main board, and $275 USD + shipping for expansions?

Features (Main Board):
-LCD Display
-200 MH/s Hashrate
-Xilinx Spartan-6 XC6SLX150 FPGA
-Standalone Functionality
-More than capable of running ucLinux (2MB Flash, 8MB SDRAM, ARM M4-Cortex MCU)
-Modular Expandability
-Reconfigurable to do as you like, not just BTC mining
-USB and Ethernet interfaces
-Maximum 4 Expansions per Main Board (Firmware Imposed)

From the sounds of it, you'd be willing to pay a little extra for some bonus functionality.  Let me go back to the drawing board a little bit, and see what I can do about offering something that does it all on-chip, so that you can plug it into your router etc. at home and have it mine without a host.  USB will remain available for those who don't have an extra port on the router, and WiFi will be an *option* too, though it'll tack on a little money.
After some review, I'd like to make it clear that there will be a maximum of 4 expansion boards per main board. (Note that a specialized jumper tech is in the works, this number may increase)  This will be a limit imposed by firmware, and you can modify it if you like, but it will be unsupported.  The price of a main board won't be *that* much more, so getting 1 GH/s per mainboard-and-four-expansions isn't too bad for the price.  Not to mention the fact that it's modular.
As far as what my offering has that others don't, the modularity and Ethernet, as someone mentioned, are a plus.  Now, standalone functionality and WiFi capability will also be a bonus.  All of this in addition to the fact that my prices are competitive, if not cheaper than the going rate for FPGA miners.
Let me lay down a schematic that allows for standalone operation and I'll let everyone know what the price is looking like, so y'all have a better idea.  Spoiler: It will be more expensive given that it is standalone, but I can tell that that would be convenient for some of you, so I'll check it out.
Keep an eye on the post, and thanks for your comments!

Well. the icarus are some sort of expansion boards, there is only the mainboard missing, and i bet ngzhang would be able to design such a board.

None of the other boards have Ethernet, and only some offer any kind of expansion - not to mention that this one is the first to offer any sort of modular expansion.

Then what would distinguish your proposed system from the X6500, Icarus, or Ztex boards already out there?  It seems to me you are just re-inventing the wheel with what you propose.  That's great if you can manage to do it for less than they are charging, though I suspect that will not be so easy. 

The board, as advertised, already has USB and Ethernet functionality and connectivity with the firmware.

Yes, perhaps an expansion card with LCD capability could be arranged, no they are not that expensive.  Perhaps I will add a communications port for peripherals that can be purchased seperately on these counts (LCD, SD, etc.) without having to include them in the project and make the whole thing more expensive.  I will not, however, impose features on people.  It will be barebones, then will have the capability to expand with whatever fancy parts you'd like to have.

watching

Peltier chips are able to cool things well, but they suck up enormous amounts of energy and spit out a heck of a lot of heat.

earlier today I was pointed in the direction of Xilinx Zynq 7000 EPP which are ARM processors with an FPGA on die, and including an accelerated SHA256 hash engine. However I couldn't determine what level the FPGA matched at.

Anybody seen this, as I've been informed a european company is doing something in this region with lots of chips on a board? I don't have any other details beyond the chip.

marked

How about using thermogenerators to power wireless and cooling fan or a peltier? Once programmed via USB then they only need to connect to a power source.
See micropelt.

You are right, and indeed I was quoting SDRAM prices.  I just edited my post to reflect this.

Such largisch SRAM is expensive, and you need several Chips,  SDRAM  would be better solution, as several MCUs have already the requiered Interface.

Why not add a USB controller (controller IC plus socket available for not more than $4 and maybe 1 square inch of board space)?  USB host mode gives you a lot of flexibility to add any device you can find or write a driver for in the future.

You can get cheap LCD displays on eBay for around $4 for a 16x2 model.  Of course you'll need some headers to mount it, but that shouldn't add more than another $2 or $3 to the price tag.

Same thing goes for an SD card socket (or microSD if you want to reduce the board space required).  Around $3 is all it costs for the socket and you don't need any other support chips that you don't already have for other circuitry.

What other peripherals?  Oh, an ethernet port.  Microchip makes some suitable controller chips for about $4 (SPI interface).  Add a socket for under $2.

The SRAM SDRAM hurts a bit more.  For 32MB (32-bit wide), we're looking at maybe $15.

So altogether that's around $35 extra in parts to the price tag to be able to run embedded Linux and thus support full standalone operation.

It occurs to me that you could make two models.  One master model which is capable of standalone operation.  One slave model which can plug into a master model and extend it's mining capacity (and save you up to $35 in parts at the same time).  Since there's no need for a high speed bus between master and slave (they would operate as separate miners), you'd have a lot of flexibility in how you implemented that as well.

Maybe as addon cards those would be suitable? People could choose which features they want included, the extra cost in base product is the added headers and design.
Would that work?

If something running without any host machine would be something you're interested in, I'll look into modifying the design.  It means it's going to probably cost a little more (not tons, but some).  It also means I'll switch over the MCU I'm using to something more effective for the job.
As far as an LCD, that's doable, as long as you understand that it's going to make it cost more.  Same with, say, WiFi compatibility.  Add about $20 per "feature" like this to the price of the unit (main board, that is).

If you're going to localize the ethernet communication to create a standalone unit, why not throw a cheap LCD and driver on the board to indicate hash rate, etc.

I would definitively prefer a stand alone unit, if it's convenient to manage.
even 20$ extra for such wouldn't matter at all, because that's saved in electricity costs of having a host to run them, nevermind cost of the host machine ...

You make a good point.  I'm just doing this because it interests me and not because I want to make money mining.  However, I would be curious to know what the folks out there who are considering using an FPGA-based solution for mining would prefer:  an FPGA that plugs into a USB or serial port and requires a host like the existing systems, or one that can also run as a standalone system, possibly even on a wireless network.  Would that be worth another $10-$20 to the price tag?

Adding an SD card interface is almost free.  For the cost of a socket (around $3) and a bit of space on the PC board you're done.  The SPI interface only needs 4 connections + power.  USB (host mode) would be nicer, but somewhat more complex as you'd probably need a USB controller.

If you're going to add an MCU to the board anyway, and if you're considering an ARM processor, then you should know that there are a number of ARM9 processors that include an MMU and can run Linux if you provide them with sufficient amounts of memory.  But I suspect you may be looking at MCUs that have fixed amounts of on-board memory which is far short of what is required to run Linux.  Actually, I'm curious to know why you'd want to have an external MCU when the FPGA is fully capable of booting itself from compatible flash memory and a soft-CPU equivalent to an AVR32 would use less than a thousand LEs?

The advantage of Linux over rolling your own custom firmware is that it saves you a lot of re-inventing the wheel, especially for standalone operation.  It will be *much* faster to develop under the Linux operating system than it would be under Atmel Studio for instance.  Linux drivers exist for a lot of hardware (ethernet/sd over spi/usb/etc.) whereas the selection in Atmel Studio (or AVR Codevision for that matter) is much more limited.  And what is the added cost anyway?  An extra watt of power dissipation?  A few dollars in parts?

I was asked about how the boards are expanded upon, and gave a short answer that summarizes the solution.  I'm well aware of the challenges that are encountered when transmitting signals.  I didn't going to go into absurd detail, but in anticipation of people getting irritated that I say that a bus is indefinitely extensible, I even said that to maintain performance there would be a limit imposed on devices per bus.  That's not to say there aren't other things in place to preserve performance, but I figured it would be sufficient to say that, at least.  Apparently it isn't, and I'll try to do better when answering questions in the future.


These I am taking into account, except for perhaps an SD card slot, but I figured the good folks around here would probably just be more interested in what I'm using for hashing, and maybe what I'm using for control, and not so much the infrastructure chips that will make it all possible.  The MCU in particular might get replaced with an AVR32 or an ARM device.  I won't be running Linux on the MCU, whatever it ends up being, because that's too much overhead.  However, given the board's specifications, I'll make sure that if people would like they can program the device with Linux, provided the resources to do so don't make the board cost anymore than it already would.

Maybe you should repeat your first years electronics course, and the influence of capacitive bus loading and line inductance on speed. Please don't forget that you have only a limited driver strength. I bet just jumper wires with many connectors inbetween and no termination will give intresting results in signal integrity.


Maybe you could ask ztex for that information. In the past he had a license production offer.

Consider adding a few extra pieces of hardware that are missing from existing FPGA mining systems in order to allow it to operate in standalone mode.  I'm talking only about some SRAM, and ethernet port, and an SD slot.  The purpose of these additions is to allow the FPGA to run Linux via a soft-processor on board.  I'm assuming you're already planning to include some flash memory to hold the bitstream so that the device can coldstart by itself.

I have used just such an approach on my Altera DE2-70 development board.  It runs no-mmu uClinux on a Nios II soft processor.  Both the Nios II and a slightly modified version of fpgaminer's FPGA mining code are loaded into the bitstream.  I've nearly completed a very simple C-based miner (no-mmu uClinux is too limited for existing miners as far as I can see).  It communicates directly with mining pools via JSON/HTTP in order to fetch work and report results.  It is all somewhat preliminary at this point, but I hope to have a fully functional system running within a week or so (albeit at a measly 25MH/s which is all I can squeeze from the DE2-70).

It should also be straightforward to get uClinux running with an MMU on an FPGA which creates a lot of flexibility and opens up a lot of possibilities in terms of customizing the system.  For example, a tiny web server could be run in order to allow the user to control and configure the system (just as is done on many consumer grade wireless routers).  In fact I will probably do this myself as soon as I finish with the no-mmu system.  BTW, uClinux runs on the Xilinx MicroBlaze soft-CPU as well.

If this is of interest and if you'd like some assistance creating it, let me know.

If you read the full description you'll see that one motherboard does not limit you to a certain number of devices.  They run on a bus, which is extensible indefinitely, at least in theory.  The bus can be connected with stacked headers, or via a jumper cable, so there's no capacity limit physically either.  There will be a firmware imposed limit to ensure performance.  Since the firmware will be open source, you'll be welcome to remove said limit.

Perhaps, if there's a lot of demand for multiple-miner boards, I'll adapt the design.  Until that time, as it's been made abundantly clear, I need to prove myself, and to do so I think a good place to start is affordable, easily extensible, single core miners.

Additionally, I'd like to know where these bulk FPGA discounts are from, I've yet to find a distributor who will give more than a pittance of a discount on large orders.

Exact control and mining hardware specifications are listed in the newly updated first post.  Specifics can be found there, but the control device will be a Microchip PIC32 and the FPGA will be a Xilinx Spartan-6 XC6SLX150 running at 200 MH/s with the current firmware.

The whole idea of a multiple FPGA units per card is to actually save money on building the cards by benefiting from bulk chip orders pricing and pass that saving to the customer, since having cards with say 10 chips would likely cost around 70% of buying 10 of the singles. If you can afford a 350+250/card starter you can easily afford an upgrade card that costs around that price. And having a 4 chip card starting around $700, $1200 for 8 and so on and forth would make more sense than buy lots of boards that give no nominal performance increase... Why pay $1000 for 800mh/s in 4 daughter cards when the BFL gets you 830~mh/s for $599 without the need to buy an additional main board to plug it in? It's very poor efficiency and not cost effective to have the performance upgrades so small, they shouldn't be less than ~500mh/s per card ideally more or you will need a warehouse to store all those little boards to get any high end performance. I am sure you can't put too many upgrade cards per motherboard either, which means you will need another $350 board to add more after a few modules upgrades, speaking of which... how many upgrade modules can your main board hold before I would have to buy another board to get more cards?

They have to do with eldentyrell (as his post said). There is no price mentioned only that eldentyrell has put many hours into the work and wants money for the time spent. But no one knows how much $$ will be needed for eldentyrell to release the code, if it's ever released. It seems that the alternative is to
have people send boards so the encrypted bitstream can be loaded. Not a very popular idea I'd say.

I would expect that all the currentt board makers based on the xilinx xl150 would really like to get 300MH/s per chip.

Did you get a refund? A horse has to win a race or two before I'd put any money on it.

Being a registered company helps in that part ^_^
You might be interested as a fellow finn what i'm thinking about doing: https://bitcointalksearch.org/topic/mining-resources-hostingleasing-service-worth-it-68634

Shipping is a minor cost, the real problem is the 23% in taxes (thats 23% of the order price including shilling) when ordering electronics from outside the Eu.

You've done that before when you asked for donations. I've counted alot on that 75MH/s from 22k altera cyclone and I donated. They are in easy to assembly TQFP package and costs 36$.

Although I'm unsure of what Silicon Valley professional rates have to do with anything here, I appreciate the suggestion regarding improving the bitstream.  I did already say that the quoted 200 MH/s was a verified, proven, base rate, and if you read reasonably you'll find most of the numbers I have right now are preliminary numbers, numbers that are a worst-case scenario, numbers that I will try to improve, but that are not inflated because I do not want to promise what I cannot deliver.

Since you are initially targeting the well-known Spartan6-150, maybe you can focus your youthful energy and enthusiasm on fitting three SHA-256 instances into the FPGA, and then fine-tuning these instances to about 100 MH/s each (300 MHs/s total), and then releasing the binary, unencrypted bitstream into the public domain.

That would make you a hero and a living legend on this forum.

While I admire Eldentyrell's technical expertise, I admit that I do have issues with his idea of getting "fully compensated" for his near genius-level optimization. Fully compensated at what hourly rate? A technical consultant (hardware, software) in Silicon Valley will typically bill at an hourly rate of $100 & up. A Silicon Valley lawyer bills at $300 & up. A psychiatrist bills at $400 & up. An anesthesiologist bills at an hourly rate of $700 & up. So, if he has invested 500 hours into this, does he expect $50,000? $100,000? $200,000? I seriously doubt that he will be able to raise amounts of this magnitude on Kickstarter, which leaves the FPGA mining community stuck at 210 MH/s (ZTEX bitstream).

Please consider it.

Compatibility and integration with existing systems are a great idea, we want this to be as versatile and easy to use as possible. There will need to be a dedicated GUI/toolkit for Nanominer, if only for configuration and use of features unique to this system. As he's mentioned, Azelphur is my man handling the software side.  He does good work and I'm lucky to be working with him.  He's the one to talk to with ideas on how to make the user experience better .

As far as 28nm technology goes, Nanominer's first iteration will not be on a 28nm chip, it wouldn't be economically feasible.  However, to answer your question, in the future when it's within a reasonable price range, we'll be more than capable of delivering miners on whatever technology is available, 28nm or otherwise.  That is, unless my research, work experience, ECE degree (in progress), and hobbies all go to waste, which I doubt they will .

And no, as to the Nano running at 75 MH/s that figure was a well meant but frankly uneducated estimate on my part.  Maybe I should say here that I'd like to apologize for promising the moon in the earlier stages of this project.  I know that people offering more than they can deliver is not something you all want to hear.  That's why, with this project, I'm offering nothing more than what I know is possible.  If you'd like to know how I came to a decision about a feature, or have a question about how I intend to achieve what I promise, please do ask.  It's all being planned out with the help of others with various areas of expertise, and always conservative estimates.  I'll be happy to release something that outperforms what I promise, but in engineering there are always unforeseen hurdles, so I'm trying to be realistic, and even a little pessimistic.

More to come...

Integration with cgminer would be really great, since it already supports the BFL Single and the Icarus, and it also supports RPC for frontend/easy remote management, if required.

No need to reinvent the wheel, I'd say!

Make the browser the GUI.  Doing a GUI any other way is not so portable plus they always require all the extra gui packages, etc.
Everyone/everything has a browser already. And keep it simple so command line tools can use it too.

Very early days yet, but I'll most likely be making the front end for this. My basic ideas for that so far are...

A python library, to enable easy communication with the miner in your own code should you want to
Command line and GUI tools (which use the library).
For the GUI I'm still not settled on a GUI framework. What ever I choose I intend for all of it to be cross platform of course. I may also make a web front end?

comments on this also welcome

I have read that the smaller-size/lower-power curve of FPGA ends with 28nm. So it seems that the 28nm designs are going to take more work than in previous generations. Is the sha-256 code required simple enough that the 28nm design won't provide new stumbling blocks and/or increase time-to-product?

wonderminer,
Were you able to get 75MH/s on a de0-nano or is that just a theoretical number? Is there a git repo somewhere?

I'm based in Canada, however I know that the demand for these boards will be international. 
My goal is to mitigate some of the shipping cost by decreasing the profit margin, like I say my goal is only to make enough to be worthwhile and pass on the rest of the savings.
As well, small form factor and an off-board power supply will also help with this, though I know this holds for most FPGA mining technologies.

Where are you based ?

..this becomes extremeley relevant when getting hardware shipped in to Eu, Finland to be more exact, automaticly adds a price of +23% for the hardwareand shipping/handling.

What is the cheapest FPGA that will work for mining, and that has a metal heat spreader? Heat is always a problem with mining, and a more efficient way to dissipate it may be worth some extra cost.

I'd also just like to make clear that an FPGA has not been chosen for this board in hopes that by the time things are ready, a chip other than the Spartan 6 might be cheaper or perform better. There are, however, candidates.

I am not planning on using a 28nm chip, either, unless something really, really unforseen happens.

In fact, so that there are no miscommunications, the current candidate FPGA device for Nanominer is an XC6SLX150.  That is subject to change.

I spoke with a distributor Friday, they're expecting late April, early May release of the Cyclone V.  However, these things change, or I may have been misinformed.  All that said, the philosophy stays the same: when the new set of chips come out, there will be either a performance bump or a price drop for us.  If the project is ready before the new chips come out, we'll start using one of the currently available candidate FPGAs and switch over later.  As stated in the initial post, this architecture supports upgraded chips via simple firmware updates.


Two important things there:
1) Making a PCB for 8 FPGAs forces people to buy in multiples of 8.  That's an expensive board.  Wouldn't you rather have the option of buying those 8 chips one at a time?
2) If you want to do the mass thing, you go ASIC, you don't buy 250K FPGAs.  When you pay for an FPGA you pay for a)performance and b)reprogrammabililty.  If you want a lot of them, and you don't need part b, you're going to save by making your own ASIC.  But that day has not come for bitcoin, not by a long shot.

It's my mission over the next while to prove we can.  I have the prototyping hardware at my disposal, so stay tuned.

The cheapest FPGA chip (best MHs/$ ratio) is the Spartan-6 LX-150 at the moment. Forget the EP4CGX15 or even the EP4CE6, first one I've used in another project. As long no one like wonderminder has any magical trick to squeeze much more out of this architecture then currently  possible, it desn't make sense. I don't know where you get the EP4CGX15 for only 6$, even in high volumes (normal price ~20$ for about ~100pcs), but if you need higher volumes of the Spartan-6 LX-150 you will also get a much better price then in low volumes.

You know (and granted I'm no expert) I've always wondered why don't fpga mining board designers just find the cheapest FPGA chip and slap a whole bunch of them on a PCB and cluster them. For example put 8 Cyclone IV chips on one board and get 600 Mh/s

But the problem may be getting them cheap enough without the need to buy them in massive bulk quantities...to quote a website: "The EP4CE6 and EP4CGX15: Starts at $3 and $6 for 250K pieces"

Anyone got $750,000 lying around?

First, I like your motivation to improve FGPA mining and don't want to frustrate you.

Just let me give you my feedback.

I'm quite sure that the Cyclone V will not be available for your project in the middle of the year.
Indeed the new 28nm FPGA's are quit interesting for mining, but it's expected that Xilinx will first get out with their Artix-7 before Altera can do with their Cyclone V.
They start the whole 28nm process-change far before Altera, and they have the very first 28nm FPGAs (e.g. Kintex-7 and Zynq) in small amounts 'available'.

And eveything looks like the new Xilinx chips (Artix-7) will not be available before at least 6-8 month, so I would not count on available Cyclone V chips before end of this year.

Current: Altera Cyclone IV vs. Xilinx Spartan-6
New: Altera Cyclone V vs. Xilinx Artix-7

Even if both new comparable FPGA series are available, we know from the current designs that the Xilinx FPGA's are more interesting for mining. Everything looks like this will also be the case with the new series.
You made very interesting announcements, that you think you will be able to squeeze out more MH/s on Cyclone IV chips (+75MH/s on a DE0 nano). How close did you already reach your expectations and who much hope did you still have to squeeze out more?  

I would wait until it is more likely that the new interesting 28nm Chips will be available soon and then think again if it still makes sense to start a project with them.

If you still have good ideas how to optimize the existing FPGA logic for mining, you can do it right away. With every new FPGA-miner the market for optimization growth.

Hope you can deliver. The price is definitely competitive.

Nanominer BitCoin Mining FPGA Platform – Coming Summer 2012


Specifications (Updated)
FPGA Mining Core: Xilinx Spartan-6 XC6SLX150 (N3FGG484C Package)
Controller Device (MCU): Microchip PIC32 (MX795F512L) [Motherboard Only]
Hashrate: 200 MH/s (per mining core)
Cores per Board: 1
Control Interface: Ethernet, USB
User Interface: PC/Linux/OSX GUI
Power Consumption (estimated): <10W
Expansion Method: Mezzanine Header Expansion Port

*Exact hardware subject to change without notice; performance will not be less than the above stated.

Design Philosophy

Open source technology:
Nanominer's schematics, parts lists, FPGA bitstreams, and source code, as well as the controller software will be freely available to all.  Want to improve it and build your own?  We encourage it!

High-tech power, low-tech simplicity:
Nanominer will ship ready to use.  Simply plug in the power supply, attach Nanominer via USB to your PC/Linux/Macintosh computer, or via Ethernet to your router/switch, start your software, and enter your details in the easy-to-use GUI.
Nanominer also ships ready to customize, with open sources and configuration via Ethernet or USB, you can tweak any aspect of the device's functionality to your heart's content.

Incremental Improvement:
A system can consist of a single board, or many, depending on what you would like to spend.  If you decide to add performance later, you can.  This also means that down the road, when new FPGA devices are released, and you want to upgrade, you can keep using the old with the new.  Nanominer version 1 will be able to have later versions plugged into it, so if you buy a main board now, that means you can keep reaping those savings far down the road.

Expansion without redundancy:
Nanominer uses a single controller and power supply for the main board, then can have additional mining cores stacked via mezzanine headers to add hashing power to your mining system.  Boards can also be daisy-chained, meaning you buy one controller board, and from then on it's just mining boards. Those savings in controller and power devices are passed on to you.

Mining should not cost the miner:
Nanominer's low wattage FPGA mining cores, extensible architecture, and small form factor mean you can mine without consuming undue space and power.  This makes mining simpler, and more profitable.

Decisions, decisions...
Nanominer is currently in the component identification stage, and some questions need to be answered.

Questions you can help us with are:
-Do you prefer Ethernet or USB as the control interface? Or are there other suggestions?
-Would you like an optional WiFi interface?
-We would like to provide a warranty on Nanominer devices; what would you as a customer like to see that warranty protect you against, and for how long?
-Is there anything else you'd like to see, functionality-wise, on this device?

Questions we're answering right now:
Q: What is the best FPGA we can put on this board?  
A: Altera's new Cyclone V device is releasing soon, and new technology means potential price drops.  This means that Nanominer may perform at more than 200 MH/s, or we may simply use an older chip at less of a cost.  Either way, time will tell.
Q: How much exactly will this cost?
A: If we were to build it now with a Spartan device, the price would be $275-300 USD for the main board, slightly less for an expansion (both 200 MH/s).  Depending on the features we do or do not include, and depending on how chip costs change with new technology being released, this figure may be less.  If we include a warranty, this figure may be more.

Finally, questions you might like to know the answer to yourself:
Q: You say 200 MH/s is the hashrate, how sure are you of this?
A: We have a number of candidate FPGAs in mind, and we're quoting 200 MH/s because we've proven that with a cost effective device, we can achieve that rate. Nanominer will not perform at less than 200 MH/s per board.  There is a possibility that it will perform better, however.

Q: Summer 2012? That's a long time to wait... why the late release?
A: Part of the reason is we're waiting for new technology to be released and prices to settle, so you get the most bang for your buck.  Once that happens, developing these things takes a lot of time and effort.  Also, I'm a university student, and my time will be much freer in the summer.

Q: You say boards can be stacked or daisy-chained? How many mining chips can I connect to one main board?
A: As far as stacking the boards, we'll recommend you don't stack more than sets of four; however it's technically up to you.  Daisy-chains require a cable that will be included.  The total number of miner cores per main board is limited only by bus performance.

Q: How accurate is that $275-$300 figure?
A: That is based on a parts order for the printing and assembly of 25 boards.  So it's very accurate for the time being.  If there's more interest, we'll make more boards, and because of bulk discounts, that price will go down.  If advances in technology this spring work to our advantage, again, that price will be reduced.  If a feature like WiFi or a warranty is added (these will be optional), that price would increase some, with obvious benefits.

Q: You mention “main boards” and “expansions”, what does this mean, exactly?
A: A Nanominer system consists of one controller board ($275-$300), and as many expansion boards (~$250) as you'd like, performing at 200 MH/s each.

Q: Does that price include cables, power supply, etc?
A: It does, and that accounts for the range.  There are a few parts we have candidates for but have not fixedly decided on.

Q: This is a pretty good price, what's the catch?
A: No catch.  Designing the system to run on a single power supply and single controller saves money.  Producing many similar boards means part discounts, and adding only my design time to the price tag means I'm only making enough profit for it all to be worthwhile.  Also, this won't be a fancy board; it'll be professional, but not flashy.  That also brings down the price some.

Thanks for reading, and please let me know what you'd like to see in this design.
As always I'm open to comments and suggestions, email, PM, or post.
Cheers!