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Topic: Open source ASIC design plans in Hardware Description Language (HDL) format? (Read 1432 times)

sr. member
Activity: 728
Merit: 256
Are there any freely-available ("open source") ASIC design plans in, e.g., HDL or AHDL format(s)? (cf. the related Bitcoin StackExchange question)

There was a project regarding this: OpenBitASIC : The Open Source Bitcoin ASIC Initiative
sr. member
Activity: 507
Merit: 253
There's several open source board designs, but no open source ASIC.
There's this, but, yes, technically FPGA ≠ ASIC.
hero member
Activity: 686
Merit: 500
FUN > ROI
Nope.  There's several open source board designs, but no open source ASIC.  Designing one for larger nodes isn't hard, you could easily do a hardcopy style from an FPGA design (that are available) - designing an efficient one is another matter of course Smiley
sr. member
Activity: 507
Merit: 253
Are there any freely-available ("open source") ASIC design plans in, e.g., HDL or AHDL format(s)? (cf. the related Bitcoin StackExchange question)
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