Cool thanks for the info I'll try to digest it. It seems that most FPGA ic's are made in Taiwan? Although this article:
http://newsroom.intel.com/community/intel_newsroom/blog/2013/02/25/altera-to-build-next-generation-high-performance-fpgas-on-intels-14-nm-tri-gate-technology
Seems to suggest 14nm ICS may yet be fabricated in "home" territories (not just the far east)
I think it's sad that we don't make anything anymore in the UK.
I'm quite excited about all this ASIC stuff but then it would be nice if the hardware remained retargetable as well as energy efficient.
I wonder if Parallela would be any good for mining?
http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone
(I recently discovered this, but after the funding had completed)
Topic: proASIC low power FPGA (Read 3316 times)
It is NOT just down to the number of gates........
Take for example the following:
XC5VLX110T = 17,280 slices
XC3S1600E 33,192 gates , 14,752 slices
A fully unrolled design fits in the XC5 ,but in the XC3 it utilizes >300% of the resources, re-rolling the algorithm produces stupidly small amounts of hashes <40MH/s
It is how the cells/slices are configured and the functionality they provide...
Sha256 is very "Rotation" and addition driven, so if your device has this logic built in, then a 32/64 bit adder unit is gonig to take up WAY less than if you implement it from 2 bit adders
Also this logic is flawed.....
[quote
Nope. Two rounds of bitcoin hashes = 132 clocks acording to this:
http://www.actel.com/products/ip/search/detail.aspx?id=627
[/quote]
If I build a massively parallel design then I can actually recover 1 hash every cycle, after an initial startup of the flow through.
I researched this because I had seen someone selling 30 XC3S1600E@$10USD each, and I had a plan..........
I also know that 'Razorfishsl' has a large XC5VLX110T array for crypto research, (RF, for the record I think you are a twat,Rgrds. the legal action... I'm keeping the Hardcorefs account...)
Take for example the following:
XC5VLX110T = 17,280 slices
XC3S1600E 33,192 gates , 14,752 slices
A fully unrolled design fits in the XC5 ,but in the XC3 it utilizes >300% of the resources, re-rolling the algorithm produces stupidly small amounts of hashes <40MH/s
It is how the cells/slices are configured and the functionality they provide...
Sha256 is very "Rotation" and addition driven, so if your device has this logic built in, then a 32/64 bit adder unit is gonig to take up WAY less than if you implement it from 2 bit adders
Also this logic is flawed.....
[quote
Nope. Two rounds of bitcoin hashes = 132 clocks acording to this:
http://www.actel.com/products/ip/search/detail.aspx?id=627
[/quote]
If I build a massively parallel design then I can actually recover 1 hash every cycle, after an initial startup of the flow through.
I researched this because I had seen someone selling 30 XC3S1600E@$10USD each, and I had a plan..........
I also know that 'Razorfishsl' has a large XC5VLX110T array for crypto research, (RF, for the record I think you are a twat,Rgrds. the legal action... I'm keeping the Hardcorefs account...)
how about this?
Cyclone® V E
http://www.digikey.com/product-detail/en/5CEBA9F23C8N/5CEBA9F23C8N-ND/3879650
$200
300k logic elements
would it roughly do about twice the output of a spartan 6 150k ?
p.s. I am an FPGA n00b in case that wasn't obvious
Cyclone® V E
http://www.digikey.com/product-detail/en/5CEBA9F23C8N/5CEBA9F23C8N-ND/3879650
$200
300k logic elements
would it roughly do about twice the output of a spartan 6 150k ?
p.s. I am an FPGA n00b in case that wasn't obvious
Nope. Two rounds of bitcoin hashes = 132 clocks acording to this:
http://www.actel.com/products/ip/search/detail.aspx?id=627
with utilization 2x15%. So only 3 bitcoin cores can be implemented there. If (VERY BIG IF) you can reach clocks around 264MHz then one core will be hashing with 2MH/s (264/132=2) * 3 cores = 6MH/s.
http://www.actel.com/products/ip/search/detail.aspx?id=627
with utilization 2x15%. So only 3 bitcoin cores can be implemented there. If (VERY BIG IF) you can reach clocks around 264MHz then one core will be hashing with 2MH/s (264/132=2) * 3 cores = 6MH/s.
6 MHs? Not a typo?
A3PE1500 - 150$ chip.
SHA 66 clock core - utilization 15%. So 6 cores per chip = 3 bitcoin cores (132 clocks per hash). Estimated hashrate 6 MH/s.
LX 150 - 157$ chip. Hashrate 250MH/s.
SHA 66 clock core - utilization 15%. So 6 cores per chip = 3 bitcoin cores (132 clocks per hash). Estimated hashrate 6 MH/s.
LX 150 - 157$ chip. Hashrate 250MH/s.
PROASIC FPGA is a compromise between ASIC and FPGA
http://www.actel.com/products/pa3/
Much Lower power consumption than SRAM FPGA.
Axcelerator FPGA can be programmed only once and looks like it's a bit faster than proASIC.
http://www.actel.com/products/axcelerator/default.aspx
IGLOO FPGA can be programmed multiple times because instead of anti-fuse, a flash cell is used. Very low power consumption.
http://www.actel.com/products/iglooseries/default.aspx
http://www.actel.com/documents/LPFPGA_FS_PIB.pdf
The largest device has 24,000 Flip Flops, or around 1/10 the size of Spartan6 LX 150
SHA-256 hashing core for proASIC
http://www.actel.com/products/ip/search/detail.aspx?id=627
http://www.actel.com/products/pa3/
Much Lower power consumption than SRAM FPGA.
Axcelerator FPGA can be programmed only once and looks like it's a bit faster than proASIC.
http://www.actel.com/products/axcelerator/default.aspx
IGLOO FPGA can be programmed multiple times because instead of anti-fuse, a flash cell is used. Very low power consumption.
http://www.actel.com/products/iglooseries/default.aspx
http://www.actel.com/documents/LPFPGA_FS_PIB.pdf
The largest device has 24,000 Flip Flops, or around 1/10 the size of Spartan6 LX 150
SHA-256 hashing core for proASIC
http://www.actel.com/products/ip/search/detail.aspx?id=627
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