Topic: Project Evil Genius – Custom SHA2-256 Circuits on a FPGA (Read 12351 times)

How much u wont for full source of sl3 unlocker for fpga ??

Thank you! Will check it out.

Regards

https://github.com/fpgaminer/sha1_collider

Hi,

Thanks! So the only chance to have performance boost is to fit 2 or more sha instances to run in parallel, but with unrolled SHA1, it might not be possible to fit it all.

BR

Max LUT speed at Spartan6 is 400MHz. Additional delays with routing and whole project runs at max 200MH.

Hi,

Is it possible to run SHA-1 in single clock cycle, similar to the SHA256 in your implementation ? And what is the max clock of
say Spartan 6 ? 1000 Mhz ? If yes, this means single xtex quad board can match a single ATI 5970, which is not that bad.

BR

Hi Doctor, any good news on the progress? In case you need access to ztex quad board, I can give you remote access to a linux VM with one or two ztex boards attached. PM me if you interested.

Sir, I just have a couple comments for you.  Since they're free, I'm certain that they will be worth every penny you have to pay for them.

First, the following dichotomy is as interesting as hundreds or thousands of similar ones we can find  spread over the last several hundred years, in all forms of technology:

fpgaminer(at post 50) : "BitFury's open source design for the Spartan 6 LX150 is already at the zenith and will not be surpassed by any meaningful margin.  That design achieves ~300MH/s ..."

DoctorDoom: "I can fit a lot more Double Hashing circuits on a LX150 chip. It looks like I will break the 1GH/s on a LX150 chip ..."

Taken at its face value, that speaks to advances and economisations you have affected in your implementation of the double hash.  If these advances are original, then that has indirect value in terms of greatly enhancing your reputation, and thereby, your human capital.

Human capital can't be spent at the store to feed one's family, though.  The problem you face is that, as the bitcoin network hash rate heads relentlessly towards 500 TH and beyond, 1 GHps on an FPGA with a wholesale or used price in the $50-range won't feed one's family, either. 

On the other hand, if you could produce an incontrovertible video of a single Spartan 6 demonstrably hashing at or near 1 GHps, then someone might determine that such functionality had direct, scalable value to them in some way.  Then, through license, or though venture, you might be able to release some of the potential value locked in your labor.

Best of luck to you.

One other point, re: the recommendation to contact the current bitcoin-asic vendors.  You worked for Intel.  Your skills, at least as self-represented, appear quite impressive.  Your world view is probably not the same as theirs.

When enterpoint rolled out their cairnsmores and was struggling with getting a well performing bitstream for them I made a bounty thread with input from the community that ended up being one of the largest on the forum to date. A bitstream was produced that met and exceeded the bounty terms and the bounty was paid out. I'd like to suggest someone does this again. This time there needs to be a larger weight on the difficulty at the time a bitstream comes out. Im afraid I do not have the time atm to champion the bounty, but I will gladly pledge a portion of what extended life (earnings) this could end up giving my Cairnsmores.

I have 100+ ztex quad boards. How about 50/50 split the profit of delta hash power until the boards no longer profitable? Currently, my operating expense is 1/3 of my farm's output. With difficulty skyrocketing, I believe my farm can only last for a few months.

Dude ever considered ALCOR or Cryogenic Institute? That can keep you motivated, second chance. Though even this may won't be necessary - Singularity/Immortality is near! See 2045.ru ...
But you will need money! Finish this shit and I hope we can gain something too in a win-win scenario. We already do.
Cheers!

How about this. Send bitstreams to early adopters with understanding that they do not share the bitstream with anyone (unless you ever decide to make it public), and they send you the earnings from the delta for 2 weeks.

Example I have 11 Ztex 1.15y (44 LX150 chips total) currently at ~9.5 GH/s. If you make it 3x = 28.5 GH/s , i would gladly pay you 19 GH/s worth of mining proceeds for 2 weeks. I would in fact point the equivalent number of boards to a pool of your choosing. Thats $30.84/day from me alone at todays difficulty, maybe by the time ur done its $10/day... maybe lesser...

I am sure im not alone in accepting this kind of offer... but this requires a leap of faith on both sides. (You trust that i donate the promissed hashrate to you, and I trust that you dont have something evil like timebombs in the bitstream)...

^ If you decide to opensource it(and provide bitstream that works with ztex firmware) , id donate a months worth of extra hash rate.

Hello DoctorDoom,

You seem late to this game !

hopefully I am pretty confident that your skills will interest one of those ASIC firms out there...(if you are what you pretend to be)

Your life is a tragedy. If it works out though, seeing your past work history...and throwing performance!

If not for you being disabled, if not for bitcoin very existence, then you could not support your family with just a little fun and spare time.Maybe even becoming "wealthy'.<- this headline is incredibly hard to believe, seems so fuckin good to be true.

Best of luck!

LainZ.

Also already job offers:


Try contacting friedcat, ngzhang, bitfury, aiwill also.

Good luck beating the other bitstreams. A lot of work has already gone into optimizing mining. And since FPGAs generate so little bitcoins now, and every day you delay finishing your bitstream that number dwindles even further, there's just not going to be any interest in paying more than a few pennies for a new bitstream.

DoctorDoom, I'm going to be straight with you.  Beyond learning/fun, there is absolutely zero reason to invest your time in optimizing a design for the Spartan 6 LX150 platforms.  As I said before, BitFury's open source design for the Spartan 6 LX150 is already at the zenith and will not be surpassed by any meaningful margin.  That design achieves ~300MH/s and should work on all existing Spartan 6 LX150 based miners (X6500, Icarus, Lancelot, Quad, etc).

I say this, because, from what I gather from your posts, you sound like an intelligent, creative, and hard working fellow.  I do not want to see those talents burned on a fruitless task.  If you're only doing this for fun/learning, then by all means continue.  But it sounds like you seek to benefit others from your work, and to profit from your work.  To achieve either or both of those goals I encourage you to focus your efforts elsewhere.

BitFury's design needs porting to the existing FPGA mining platforms.  It's really minimal work, and would boost everyone's performance by 50%.  That would benefit people very immediately, and I'm sure people would pay you for it.

Or you could focus on a strictly ASIC design, an scrypt miner, SL3 cracker, etc.  There are plenty of fruitful opportunities around.

Sorry if this post sounds malicious.  That is not my intention.  I'm not normally this blunt, but I've seen one too many threads like this.

Yes you are. By patenting a new process, you're removing that process from the world for 20 years. No one can use it, release it or do anything else with it without giving you money.

Doom,

Thanks for the work you put into this. I think it is great that the FPGa guys may be able to extend the life of their rigs, I for one would pay if its a reasonable cost to have an upgrade done. Thanks for your efforts and I hope it takes off.

Damn I must believe in capitalism I am willing to pay for something. GASP!!

This community rewards good deeds with donations, not forced patent license fees. Do you really think anyone will pay you when you require a fee? No thanks, first person to get the tweaks will leak all over the internet. Have fun trying to collect a dime.

@DoctorDoom

Please consider implementing SHA1 salted algorhytm also, for bruteforce SL3 logs.
And I hope that You WILL MAKE MONEY with this. I wish you to be like that.

There is nothing wrong to make money with inventions. Nikola Tesla had a lot of great ideas, but he did not make any money on them. So what happened is that he had to beg for money to keep projects running and most of them are never finished. And biggest looser was a mankind.

Itaniums had $hitty performance for all our X86 code, even recompiled with icc. Personal experience on SGI ALtix Itanium2 based servers. I think it was an EPIC sic. fail

My live code for my DE0-Nano board is actually using a 0.5MBit scratchpad (the EP4CE22 chip only has 600kBit ram), so I have to interpolate the missing half of the scratchpad (basically one extra pass through the salsa-mix for half the addresses). I can't really see how I can parallelise this as each ram read address depends on the results of the prior salsa-mix (scrypt was explicitly designed to be awkward to parallelise). From some reading I've seen that a larger scratchpad eg 8MBit can speed up the scrypt, which I don't quite understand yet, so once I've read up some more on it then perhaps some tricks will be apparent (yeah, I just wanted to get something running quickly so I coded a direct analog of the cgminer CPU scrypt.c code, rather than doing my research first  )

The pipelining of the salsa-mix is definitely an issue, but its tricky due to the dependency of the scratchpad reads on addresses generated from the prior salsa. Adding extra register stages allows a faster clock, but needs extra clock cycles to complete, completely cancelling out any gain (and there is no gain from the pipelining itself due to the address dependancy). Once I understand the algorithm better, perhaps I can come up with a solution (I'll need to take a look at the CUDA code to see what's done on the GPUs).

Thanks for the kind words, and good luck.

hi

on wich fpga you ll use as basis ?

maybe it ll be interesting to make an asic from your fpga vhdl if it gives better hashing power so we ll be able to get a more powerful asic

keep us posted

OMG he's been outed as a Capitalist!  Someone kill him before he gets away!   

Improving on stuff and making a profit from his efforts!  This cannot be endured...

 

Guys you do realise he is trying to improve FPGA efficiency, and patent the results? This is a hell of a long way from open source.

your work is appreciated, im going to run mine until it costs more in power than its worth just to contribute to the network.

I'm running the core at 25MHz (it didn't seem worth pipelining the salsa mix, given that scrypt is essentially a serial algorithm, so I've implemented it as one huge combinatorial tree), and clocking the on-chip ram at the same speed (just to keep it simple). Using the on-chip ram makes the ram interface very simple as its just a 1024bit wide data path. External RAM (as would be needed for to get any sort of performance from the fpga) is going to be more complicated and would need to run faster, which might make pipelining the salsa worthwhile. Bear in mind that I'm a complete amateur with FPGA/logic design, so don't expect anything sophisticated 

Anyway you can take a look at my code here https://github.com/kramble/FPGA-Litecoin-Miner any suggestions would be welcome. I created a thread to discuss it earlier today in the altcoins section https://bitcointalksearch.org/topic/ann-open-source-fpga-litecoin-miner-260598

That's awesome kudos to you. Would it be possible to load it on github so others can also try to use  your scrypt miner?

Jasinlee has a project running at http://ltcfpga.com/ which seems fairly advanced (but NOT opensource)

I'm currently working on an opensource implementation (just for the LOLs), using the on-chip FPGA ram (it needs 1Mbit per hasher core). I've got the simulation running fine using a register array for ram. Unfortunately I'm only estimating around 1khash/sec performance per hasher core. The next step is to port it to my DE0-Nano board (it can only fit half the scratchpad, so its going to interpolate which is even slower). I'll post it on my github once its in a presentable state.

Okay got it. Sometimes the synthesis software can also do logic optimization, which could reduce the size of hardware, though it's very rarely succesful in substantiial reduction of hand optimized designs.

May I ask did you obtain the size reduction on a HDL module or was it something else?

Watching, good luck with this. 

Only if you were here a year ago, now this is a bit late if not obsolete very soon. I'm hoping the best and I'm very interested to see how well you manage to do with this project.

I'd also be very interested in a git, and I'd certainly throw a tip your direction.

If this does work you should be able to get twice the engines into one FPGA. There is money in this as there are plenty of FPGAs out there and I'm sure ppl would love to double thier hash rate!!

Great, keep going!

Memory is problem. He will

Is there a compiled bitstream compatible with ztex out there?

FPGAMINER

Getting SL3 unlock to FPGA miners would give them new life. I do not have much of them but they will be more universal if someone keeps them running SL3.

Also I am not rich, but willing to support job with some BTCs.

It's a lot of fun down there!  It's a shame the Spartan 6 architecture is so limited.  I suggest you take a look at the 7-series FPGAs, like the Kintex or Artix.  The architecture is nicer, and performance is much higher.  For example, I was able to implement a miner using the DSP48E1s on a Kintex.

Also, have you looked at bitfury's code?  He has the most performant code for Spartan-6 LX150 chips, and I would be shocked if anyone beat his record (in MH/s) on that chip.  It's optimized down at the slice level and manually placed.  https://bitcointalk.org/index.php?topic=228677.msg2417706#msg2417706

Unfortunately, or fortunately (depending on how you look at it), FPGA's will never beat ASICs in terms of performance per dollar, or performance per Watt.  So FPGA mining is a curiosity and plan-B sort of thing now.

I coded up a quick SL3 cracker about a year ago.  It either ran on my Spartan 6 devkit, or the X6500, I can't recall.  I could probably dump the code to github if people are interested.  I didn't optimize it particularly well, just got it working.

Yes, with pleasure:

http://hashcat.net/wiki/doku.php?id=cracking_sl3

It is pretty good explained.

It is little modified salted SHA1 algo and should be around 5 times faster than algo used for BTC.
For sure it is possible to implement on FPGA. But there is a lot of pro guys with already done solution, not willing to share their work.

Atom (admin and creator of Hashcat and OCLHashcat) is great guy and very skillful programmer, he did a LOT of optimization on crypto algos, maybe he could do even more if someone gets his attention.

Any URL listing the problem? It looks interesting.

It's pretty obvious it's not converted C code, if you are talking about an automated C-to-HDL program. Those spit out garbage code. The Open Source code is human-readable - therefore not machine generated.

Good luck. Personally I doubt there is much performance left on the table by the open source code, but please prove us wrong.

You mean https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner?  That's not converted C.

Watching...

Maybe a good idea will also be implenmentig salted SHA1 algo for Nokia SL3 unlocking by bruteforce method.

What would you define as "really great results"?

+100

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

e