Topic: Re: Stratix-5 A7 or D5 project 01.05.2013 update (Read 6610 times)

Start project with fresh asic chip? how long would it take 2 produce the chip? 2014?

Kewl

Mods please close this topic, I will open another one because I decided to start the project with a fresh ASIC chip.
New topic will be open as soon as I have a team ready. Probably all EU located.
Thanks again for help and my best wishes for all!

I have only mentioned, but not for my project. Thanks for a good luck, I think I need it.

You did mention Cyclones in post #83. It's even quoted in your message. But as I said I could not understand that sentence, e.g. if you refer to Cyclones in your own project or in some other project.  Anyways, good luck on your project.

I have contacted other 2 companies for more information about their chips.
I have some helpers here from the forum for the design and testing part -> so something is moving here also

No, no never mentioned Cyclones so stay tunned on this post.

That's what I thought too, but I got a little confused parsing your sentence regarding the Cyclones. But as I said initially 60W is a lot for a single FPGA.

I'm not talking about Cyclone, but Stratix V

Then you should forward my message above to this person.


60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

Well in this case he's wanting to implement FPGA's that nobody has used for mining yet (to our knowledge) mainly because of their cost. So that's why I'm curious where he's getting these numbers, because 60W for a FPGA is a lot.

And if you're getting this info from a person, either have them join the forums or give you information that you can quote. I don't like empty numbers without some amount of backing.

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.
I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

Actually it's the software which will tell you your hashing performance, not the hardware.

Using your current hardware to check how fast it will run is risky as you don't know the process parameters of the particular part you have in the lab. It might be way faster than it's labeled speed grade. Your next production batch might not be.

Run the RTL code through Quartus. Then you run static timing analysis in Quartus and it will tell you the max clock frequency the slowest part will operate at. Multiply this with the number of hash operation the architecture can perform on each clock and you have your hash rate.

Or you have to make a design which will dynamically increase the clock speed until it fails to calculate nonces and then step down the clock until it starts to produce correct results. This is more complex as you have to make sure that timing errors don't propagate into your safe clock domain. It's also more complex to make sure your thermal solution can handle this behavior.

For power you should run a simulation of the full implementation of the design and generate a VCD (Value Change Dump) file which will show the toggle rate for all the nets in the design. This can be included in a power analysis tool like PowerPlay. This will give you a good estimate of the power consumption of the FPGA.

60W sounds like a lot for a single FPGA.

Well where are you getting the estimates? Or are you just speculating on numbers? I'd like real numbers too.

If you hire a skilled engineer who knows how to do the simulations those  numbers should be acurate enough. At least you could  see how many cores fit into  this or that fpga  etc. BTW its very unlikely that your  hwdeveloper has not some hardware  to test the design. 'Exact' numbers would also depend on the schematic for the power supply which may be different from the one used on the development board.

I wonder the NDA allows you to disclose  you have to pay 80 BTC, as  prices are usually also subject to NDAs.

OK let's try this a different way:

what is the exact hash rate and power consumption reported by the tools for your current HDL design?

In other words, what are the exact numbers the tools are projecting for you right now?

I understand everything, but software is software and real tests are real tests.
As I said the hasrate is 1-3ghash/s, maybe little more, and the power usage is something near 60W, but I would like to put exact numbers.
With the software I don't think I could get exact numbers.

In case you did not understand my previous post, you do not need real hardware to get those answers.   The actual real world numbers will vary a bit (small percentage), but certainly the tools provide enough information for you to figure out if the project is even worth building real hardware for.

(hash rate, power, unit cost)

Obviously, since unit cost is in several thousand dollar range, the hash rate and power consumption from your analysis would need to be compelling to be marketable.

I know and I agree with you. But I don't like to say for example:
New BTC/LTC machine with xy hashrate using yz power and than when I start selling, sorry people I give you wrong hashing numbers and wrong power usage.
I would like to be honest with everyone. I know that I'm asking too much, but I would like to do a project and be proud that I'm not one of the scammers who would like to sell something that doesn't exists.
I said that I'm doing a new project from scratch, before I get some answers from some company, so everything changed.

And when I will start selling, I will start selling on the date written!

I want write the real hash numbers and power usage!

Sorry, but for what it's worth, this is not customary and since you have already declared you don't have any experience developing anything (let alone HDL or boards with high end FPGA on them), asking for 80BTC in donations might diminish people confidence in you.

You may want to defer asking for donations until you have demonstrated that your plan is more fully thought through, and that you have the capability to produce something.  There is already a lot of people on here angry at multiple organizations for taking their money and not producing anything 6 months / 1 year / 18 months later.

Again, IMHO, you don't actually need to have physical hardware until you want to establish the (marginal) performance gains you'll get through overclocking/cooling in the real world.  Under normal conditions, the reports from the tools are accurate enough.

I have an NDA with the company, so I can't say which board will be used. Sorry.
I was asking the company if I can remotelly connect on the machine for 2 days and test, the answer was NO way.
So I'm trying to do my best to collect the money...
I would like to start this project, because Is not only for BTC mining.

I'm sorry, I don't understand what you are saying.

I thought you were asking for donations of 80BTC to purchase (2) development boards for your own use during development.  Is that true?  If so, what development board do you want to purchase?

If you already understood my question, then I don't understand your response: can you rephrase it?

This will be write when the machines will be ready to ship.

What board are you looking to purchase?

I have a request -> I have to collect 80 BTC for get 2 development boards
So anybody who will help me, if he will order a machine, he will get a discount price. Hope is fair enough.

I have to test, but I think also LTC mining will be possible   because of some memory (he he)

So if any of you could help me, that I go on with tests, I would be more than happy.

No, it doesn't work with Google Sheets.  It depends heavily on Excel Macros.

My interest in other cryptocurrencies is 0 so my idea is only for Bitcoin...

Power estimator nicely opens in google docs, but I have no idea how to simulate. There's no cell to input frequency or number of LEs.

No problem. But you would probably get better response regarding your interest in litecoins in a thread entitled "FPGA's and litecoins" or similar.

Oh yes I apologize, I was just mentioning that if he invests capital into an FPGA miner for bitcoins, that he always has the option to fall back on FGPA's because they are re-programmable. Wasn't trying to stray too far off topic.


Yes I do. I'll query there about many things. (See above statement).

Did you ever get a decent quote on those chips? If you really do get a decent price I'd like to buy a few up to play with. Simulations can only do you so much.

Where are you coming up with a power estimate? If it's of any use to you, Altera has a Power Estimator spreasheet you can use. I think you'll need Microsoft Office. It locks up consistently with LibreOffice or OpenOffice. http://www.altera.com/support/devices/estimator/pow-powerplay.jsp

But he has to put on alternative coin part of the forum

I have changed because I will not use Virtex so is why.
Yesterday I find a good post on another forum and I can't find it again, yeah It was on my laptop.... Lol
So in next weeks I will probably buy some chips and test.
The power usage is about 60W per chip, maybe little less.

Actually my request to start a new thread was directed to Signus regarding a new thread about litecoin FPGA mining and keeping this thread more on topic.

I will start a new thread when I will heve more information of all the things; Materials, videos, will be posted....
I don't want figure out as someone who is only talking bullshit.
I have ideas and If I see that I can move to the next level, I will, If no. I will say, thanks for help. The project is dead

I love that modern FPGA's have the capability for memory extensions. Implement a memory controller and then you can essentially fine tune the process later, given you'll need to write a test bench to ensure that you can actually read/write all blocks of memory correctly. Then you can sort out how to implement scrypt into the equation.

I'm not quite sure either as far as that goes. I need to read into it a little more.

Regardless, funnow, FPGA still has a future in either application, and really any application. That is why FPGA's are so widely used. I would definitely learn how to build a FPGA solution for BTC, that will get you started. And once you learn the basics of FPGA's, Verilog, Simulations, PCB Design, etc., then start learning how you may implement a scrypt bitstream into an FPGA.

You would probably get better response if you started a new thread about this subject.

FPGA's have internal memory. The size is limited, but the memory access has very low latency. Further it's no problem to add external DDR3 or other types of external memory to the FPGA. Most modern FPGA's will typically contain one or more hard memory controllers.

I don't know anything about the memory access pattern of a litecoin application, but I got the impression that it's basically a large cache. You could treat all the internal memory as a cache with low latency access for the external DDR3 memory. The good thing about the FPGA is that you could potentially tune the cache replacement algorithm towards the application, which is something that would be difficult on a CPU. However, I don't know much about scrypt so I can't be more specific.

Haha, I believe those chips could perform quite adequately. The paper written for Litecoin applications was written a while ago, and we're talking about new FPGA technology, even though yes the more memory the better for scrypt.

Granted nobody has developed a legitimate and power efficient method for mining LTC with FPGA's. What I'm saying is FPGA's give you that opportunity if need be, so that you're not wasting time designing the hardware for something.

Sorry but It will not have any memory so no LTC mining that's all

Well FPGA's are reprogrammable. A well thought out design could easily be programmed to do BTC and then be flashed to do scrypt for LTC.

It's difficult to compare FPGA families since the members of the families are available in different sizes and speed grades. It might be that they have compared the fastest/biggest devices in each family though. Still they should tell you exactly which device they have compared. It might be that they have used a different design than the one I've tested. It might be that they have used different optimizations for the different devices. It might also be that they have done a general comparison from other designs and used that to estimate the hashing speed for the various devices. So everybody could be telling you the truth, but all the parameters for the given results have not been given.

Also note that the Stratix V device I used was not the faster nor the biggest available.

I don't know why you ruled out the Virtex7. I just gave the biggest member (xc7v2000t) of the Virtex7 family a run through Vivado. I constrained the clocks at 200MHz and the timing was reported as 4.575ns or 218Mhz. The utilization of a single core was


Hence it might be possible to fit 27 hash cores (- logic to communicate with the cores) in the device which would lead to a hashing performance of 5.8Gh/s assuming timing would be the same for 27 cores. Others on the forum have optimized the design using the Xilinx DSP blocks (this device has 2160 of them) and did run the Kintex7 at much higher frequencies.  This is a very expensive FPGA. But again, I don't know what kind of deal you can get.
[/quote]
Kintex VII is slower the 410 series is about 1Gh/s
Virtex VII 1-3Gh/s
Stratix V +5%  more

Those details I get from some companies doing lot with chips. So why they would tell me something that is not true?

You could be curious, and you will remain curious, because It's a bitcoin project.

I don't know why you ruled out the Virtex7. I just gave the biggest member (xc7v2000t) of the Virtex7 family a run through Vivado. I constrained the clocks at 200MHz and the timing was reported as 4.575ns or 218Mhz. The utilization of a single core was


Hence it might be possible to fit 27 hash cores (- logic to communicate with the cores) in the device which would lead to a hashing performance of 5.8Gh/s assuming timing would be the same for 27 cores. Others on the forum have optimized the design using the Xilinx DSP blocks (this device has 2160 of them) and did run the Kintex7 at much higher frequencies.  This is a very expensive FPGA. But again, I don't know what kind of deal you can get.

It sounds like you have since sorted it out, but yes I was using a cloned DE2-115 project which refers to the common ../../src/xxx.v

I just changed the target device and created a new PLL.

I would be very curious to know what khash/s it could achieve for LTC. Nobody has (atleast in public) claimed to be mining LTC with FPGA.

I dont know much about FPGA or embedded programming, but from what i read, scrypt is very sensitive to the amount of fast RAM available to the cores.. The new expensive FPGAs apparently have them in abundance..

Further reading: http://bitcoin.stackexchange.com/questions/1305/what-features-of-scrypt-make-tenebrix-gpu-resistant

No problem. I did not expect to get payed. These are very expensive FPGA's. In general the cheaper FPGA's will usually get you higher H/s/$. But of course I don't know what kind of deal you can get.

I checked my design and my clock was not properly constrained due to a syntax error in my SDC file. I ran it with the corrected SDC file.The result is still not great: 185.84 MHz. Again, it was the plain unrolled design from the "rtl" directory without any specific optimization. However, the speed difference could be due to the difference between the C1 and the C2 device.

kingcoin -> for now I can only say thank you. I have to talk with some potential investors in the project, so for now I can't pay you for your help.

BTW: was this the design found in the rtl directory or in some of the projects?

I will try to re-run it as my timing result can't be correct...

I have a serial interface and some other communication logic in there which can explain the extra ALM's.

200MHz Fmax on the hash clock? That's more what I would expect, or even faster for such a device. Did you use derive_pll_clocks and derive_clock_uncertainty in the SDC file for your timing analysis?

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.
The only change I made was a new PLL megafunction.

Thanks for help.
It will be not easy to develop a good pcb... I have a friend who knows something about FPGA, but He is busy with other projects.

A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device                          ; 5SGXEA7K2F40C2                            ;
; Logic utilization (in ALMs)     ; 32,617 / 234,720 ( 14 % )                 ;

In this device you should fit at least 6 miners, more if you can share resources and use the dsp blocks.

A 10ns clock gives a slack of  -1.9ns, which pretty bad performance. I don't understand why.

1) git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git

Before you start making a PCB you should get the tools to explore implementations and do simulations to make sure your implementation is working, also you would probably want to get a dev kit to play with before you design your own PCB. They come with schematics so you can see how things are done, even though that they are somewhat overengineered and have lots of stuff you don't need like serdes, pcie, ddr3 interfaces and so on.

Virtex-7 -> It will not be used!
So Stratix V A7 or maybe Stratix V D5 -> will be used

Sorry brainfart. Which chip in the Virtex7 and StratixV families did you have in mind?

I'm not sure what he means either. I think only Stratix V is the newest model.


Okay, and I would love to be of assistance, I have experience with FPGA's and embedded design. Just not the funds to get my hands on good equipment. Even my University won't buy me anything good for my research.

If he finds you a good rate, let me know. I have heard a lot of people ordering chips or FPGA's from HK and so much so that it's almost ridiculous the kind of savings they're getting. I want to know because I'll be investing a lot of money developing FPGA's in the future.

Did I miss something? Are those new chips? Never mentioned any Arria series chip. And nowhere is mentioned Stratix - VII

Which Stratix7 and ArriaV do you have in mind?

I have a little experience in handling electronics, much more I have in computer repairing (about 30 years) but If I will need someone, there is a friend company doing this and they probably help me. Yeah similar prices, but Stratix-5 +5% of hashrate and little more power usage,...
I have sources in CHN (one of my friends moved in China) so If I find any good price, he checks the company,..... Single chip will be bought only for test, but I'm still doing some research about this part.
And as I see maybe my post is somehow interesting (see a lot of you is reading this) -> also helping me, and I can only say thanks.
Maybe the first batch will be about 15k, maybe more. But first I have to find some computer for gold refining (lol) to have a bigger $ cap (he he)

I do understand, and it's fine to learn.

Do you have any experience handling electronics? If not, I suggest reading up on soldering SMT and through-hole components. And one of my favorite books for FPGA's is Embedded Design Using Programmable Gate Arrays by Dennis Silage. Very useful.

Both chips are roughly the same price, aside from the distributors. How many chips do you plan on buying? Minimal quantities will run you thousands per chip. My sources on that one are Digikey and Altera.

If you buy 25k I imagine you can get them at a fraction of the cost, but buying a single chip would break bank unless you're rolling in dough, haha.

I have excluded Virtex-7, so the project will be with Stratix-5. And if I'm not or I don't have an Engineer, It doesn't mean that I can't do a project
And believe me the price would not be high.

Well my point is that you not an Engineer nor do you have one, and yet you're thinking about investing thousands of dollars on a product you have no idea how to design? The Virtex-7 and Stratix-5 are very expensive chips, and the only way you can afford them per chip is to by them tens of thousands at a time. Assuming you have a design in the first place.

Even without being an Engineer you should realize the pricepoint of what you want to do is very very high.

I agree too, but first I have to test and see the results.

And please people don't send me PM regarding chip offers, because I have serious suppliers and I don't want waste money in untrustable persons

lame.duck is right, it all depends.

On the low end at least 1800 MH/s, on the high end you won't know until someone does it.

The conclusion is that Stratix-5 is little bit faster but more power usage.
I think I will wait to test the chip and post the results. If such good, I will move the project forward.
Thanks to all who are helping me.
Wish me good luck

I'm not an engineer and I don't have any. No problem, we are human and we have to make mistakes.
Yeah Virtex-7 is a good one. And Kintex-7? It could be possible the 7K410T series could make about 750mhash/s?
Thanks again.

Yeah for some reason I was thinking Spartan 6, was half asleep.

As far as the Virtex-7 goes, and the bandwith that chip is capable of it can produce roughly ~1GH/s to maybe 3GH/s. It's a very beefy chip, and also very expensive. I'm talking $4000 a chip.

The Stratix 5 I'm not quite sure. I don't see any numbers as far as chip bandwidth goes, but it's outrageously expensive per chip as well.

So I don't know how low of a price you're trying to negotiate, or where from. I'm curious as to why you would consider the investment if you aren't an Engineer or don't have one?

150-300MH/s only?? I'm not talking about Spartan-6....

I'm still alone, I only have an idea, no team, no engineer....

at the end of the day is always how many hash rate per chip and at what price is the chip that counts...

For those who are developing anything at all, they have better chances learning how to develop FPGA dev boards if they don't have a few years of Engineering or tinkering under their belt. While those Avalon chips are a steal, and I might buy a few soon, I'd like to get documentation about them, and what their requirements are before I go and build an ASIC rig for myself.

Not too many people have a deep understanding of the Avalon chips, so for most people it's not a good idea to buy them up before they know what to do with them.



I would assume between 150-300MH/s per chip. The hashrate depends on a number of things. Firstly it depends on the clock rate you set the FPGA at, and secondly it depends on the bitstream you program into the FPGA.

Do you have experience with FPGA's at all?

Well, depends on how skilled your engineer is. Please compare the range of the  bitstreams for teh spartan6 which  spans 200 MHash/s to ?300? MHash/s.

you can order a dev kit, but they cost some money

Yeah, okay. But I can't answer If I don't have the primary answer: does anybody know the hashrate of Stratix V A7 or D5?
So with this information I could answer more....

Avalon Asic run at 282mh/s and only cost $8, so let say with 6 chip/ 1692mh/s is only --- $48, would you be able to beat this price

I'm still negotiating about the price, but now I need information about Stratix V A7 or D5 hasrate and power usage. If anyone has any information It would be great.
Those are only a pre development questions.

How low are you talking per-chip that you can get?

If I only could know the hashrate of Stratix-V A7 or D5 I could write more details about my project.

Had the same idea a while ago, did some research, but fpga does not intrest me that much anymore.

The world is an expensive place, saying thanks is enough for me.

Tyger thanks a lot, is a virtual beer enough for your help?

Try the open source cyclone bitstream? (https://bitcointalksearch.org/topic/official-open-source-fpga-bitcoin-miner-last-update-april-14th-2013-9047) or ask for a modified TML:
http://www.tricone-mining.com/

Seems I can get better price for Stratix V A7 or D5. So I will need help for one of this chip to get maximum hashrate. Any idea?

The discussion is about FPGA, not video cards. So please no off topic posts.

A few hundred dollar video card will give you that kind of hash rate, obviously it will chew a lot more power but still.  FPGA chips seem overpriced, probably not enough competition.

Hm do you think is posseble go more than 1Gh/s.

And because my idea is something like BTC & LTC mining, I will probably need a team, but first I have to get the price.

So any helper for 1Gb/S bitstream or higher? 

I'd want closer to 2GH for a $1k part to even bother at this stage of the game really. I'm interested in the price too though.

I will probably go for 1000+ to reduce price.

1Gh/S would be nice. Anyone knows how much W is consuming??

Thanks for your help.

let us know they price, i wouldn't mind paying 120% plus shipping depending on price

Here https://bitcointalksearch.org/topic/m.1842040 fpgaminer achieved 400MH/s with XC7K325T part. It's 1k$ part. There's a chance that he will get closer to 1GH/s. Worth it?

Sorry I'm not a programmer, so in this part I will need a help

Fire up ISE and compile the open source Bitcoin miner for them and see what is has to say for timings/usage. See https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner

Thanks a lot for your answer
Probably I will use Kintex-7 > I'm waiting for a price for 500-1000 pcs> anybody done a bitstream?

An update as soon I get the price.

I think only few ppl have experience with both of these FPGAs.

120 views and no answer? 

Virtex-7 I read that has potential of 1600mhash/s, but I don't know the hashrate of Stratix-5.

I could get both chips for low price.

Thanks in advance for your help.