No word on that.
I agree that Artix-200 will be the FPGA of choice for mining, and the $64,000 question is whether anyone (hint, hint) can fit all 125 stages of a miner into the Artix-200's 156 columns, from left to right (or from right to left), without the dreaded U-turn.
Or, to be more precise, whether anyone (hint, hint) can get all 2 x 125 stages of TWO miners into it.
The two "parks" (Central Park and Golden Gate Park) for the ADC and the PCIe controller in the left half of Artix-200 certainly don't help with such an endeavor...
Yes, there is! There was a talk just on designing power supplies for -7 chips (Artix, Kintex, Virtex) and this point was stressed. However, most DC-DC controllers have an enable pin, thus enforcing a well-defined power-up sequence is actually quite easy.
Not so easy for power-down, but while the power-down sequence is NOMINALLY the reverse power-up sequence, it isn't critical in practice (because the "wrong" condition will only last for a short period of time, not long enough to cause damage).
There is a datasheet note that states: "On power-down, voltage w may only be higher than voltage x by y volts for z milliseconds, otherwise the long-term reliability of the chip will be affected", but the lecturer said, this is almost implicitly guaranteed in most designs and should not be of concern to most people.
I sure hope not!
But I agree with you: While Intel is now shipping 22 nm CPUs in volume, TSMC still hasn't solved the problems with the 28 nm process. Sigh.