Correct, I since read that elsewhere. Even I cant always be right
Thanks.
When you do a full-custom chip design, you actually specify the locations and sizes of the components of the transistors (source, gate, drain, etc)
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Die Efficiency (GH/cm3)
Process (nm) Perf (GH/s) Die Size (mm2) Raw Normalized (55nm)*
ASICMiner 130 0.33 21.70 1.5 8.5
Avalon 110 0.28 16.13 1.7 6.9
BFL 65 4.00 56.25 7.1 9.9
Bitfury 55 3.00 14.44 20.8 20.8
Hashfast 28 400.00 324.00 123.5 32.0
Die Efficiency (GH/cm3)
Process (nm) Perf (GH/s) Die Size (mm2) Raw Normalized (55nm)*
ASICMiner 130 0.33 21.70 1.5 8.5
Avalon 110 0.28 16.13 1.7 6.9
BFL 65 4.00 56.25 7.1 9.9
Bitfury 55 3.00 14.44 20.8 20.8
Hashfast 28 400.00 324.00 123.5 32.0