@pizza's OP:
For a typical new-tech ASIC, 600k-1M seems reasonable.
I have been through a couple ASIC design cycles at my last job (longwave data receiver, which is arguably much different than a purely digital ASIC like Avalon's/BFL's). As the company was small, as an engineer I was also part of the budget meetings. It cost roughly 1M to get to our first working ASIC wafer. 400-500k went to development and the engineering runs of chips. First, everything was "simulated" on a mix of FPGA hardware (for the digital side of things) and analog hardware (for signal reception/analog side of things). About 250k went into the first two engineering wafers (first prototype batch, first revision batch), and the remaining amount 250k-ish went into manufacturing 10k chips + verification and validation hardware. Built into these numbers is roughly 1 year of employee salaries (there were roughly 10 of us working on this stuff).
So yeah TL;DR is 1M total, where 50% is employee costs, 50% is manufacturing costs (including ASIC fab and PCBs and whatnot).
so can digital ASIC like Avalon be done for much less?
My guess is yes, since the whole of whats inside a digital ASIC can be done fully on an FPGA first (hence less time/effort in producing PCBs to test analog sections). The only difference is that a FPGA would be less efficient than an ASIC would end up being (obviously). But this can all be accurately simulated.
So chop my numbers in half and they start approaching the Avalon pre-order range.
[edit] Ah, so based on what BkkCoins said, he had a little capital from the Icarus project. Add that to preorders cash and previous FPGA bitstreams, and he probably developed the Avalon ASIC for 250k or less.
