My impression was that ASIC designs are foundry-specific. How do you open-source that? Even if you published the Verilog, what good would it do?
ASIC designs are technology specific but not tied to any machine calibration. They should open source the functional verilog as well as the full mask and specification - a turn key design.
Dude,
Let us focus with simple things first.
They have announce that they will sell chips in bulk. If they publish the PCB designs (Asic Board+Controller +PDU + Components list), It will be more than enough. I do not se a reason why they shall not to do it as long this design is related with their chip. If They do that I am about to buy bulk chips and build my own units and most of us can do. I will bevery happy to do that personaly
What about that Ngzhang, Bitsync - I have mailed you a couple of times and no response still
That may be good enough for you but still misses the ethos of open source. While they scramble to get their avalons out the door, others could be doing large production runs of the same design or working on extending the original design. This is the whole point of open source hardware. Yifu says he wants decentralised mining competition, I call his bluff. If he doesnt open source it, he was in it for the money all along.
