LUT's in FPGA's are basically small RAM blocks. That's why you can program any logical function into it. So, this technology isn't designed to build SHA ASICS but it should be possible to build one. But I doubt it could have any advantage over regular ASIC.
First, I'm not sure that XPoint works for SRAMs to begin with. Not sure about block RAM elements.
There's not really that much of a benefit to LUTs since they're quite small. A LUT4 (as on older architectures such as spartan3e) contains 16 bits in a LUT, meaning 128 bits per CLB. Even newer architectures have around 64 bits in a LUT6, such as Xilinx 7 series. Making LUTs denser won't help since there are tons of other components such as dedicated gates, single registers, carry chain multiplexers, and so on.
There are some optimizations in which a synchronously used function is implemented in a block RAM. It's more important to make faster routing and CLBs, as well as more CLBs.
