Topic: 55nm Bitfury chips - Direct 220V Project (Read 3834 times)

Nice!

Glad to see somebody is still doing it.

I have finally received the boards from the assembly house



Hope to test them (one by one at low voltages) this weekend and that there will be no bad chips. There are still some unpopulated chips left, but repairs are difficult

Right, I've got a whole box of 470uF 250V pulls from old supplies. I got a box of retired (working) Dell server supplies I could scrounge some 330uF 450V Nichicons out of if you're interested.

I see the point of reducing losses, but as noted earlier, the nonlinearity in your rectifier is gonna give you a pretty terrible power factor. Course, for just a test, that's probably not too bad. I'm looking forward to your results with an Active PFC load. I actually suggested something similar to a guy a couple years ago who was trying to figure out how to chain S5s onto a 277V line.

Yes, that was the initial idea, but I have checked few broken ATX supplies (350-450W nothing more powerful ) at hand and they are all with 370uF 250V capacitors, so will need even more of them.
Also there is a risk with used ones, because their state is unknown.

The inductors in the passive PFC will increase the losses in addition to reducing the ripple currents, while I want to reduce the losses at minimum.
The choice for 450V is to be able to test with active PFC later and the increased capacitance will reduce the voltage ripple there too even if unnecessary.

There is one more advantage with multiple 100uF capacitors actually - will be able to test the effect of different values (voltage ripple) on the hashrate and stability.

Ever think about just stealing the passive PFC rectifier/cap portion out of an old ATX supply? Seems like that's most of what you're trying to build anyway, and around a 400W supply should be input-rated for your draw.

Small update.

While waiting for the assembly house to populate the boards ( slow cheap order 2+ weeks to wait ) I have started with the power part and the sad thing is that, even we need just 330uF capacitor it can't survive the RMS currents, so instead of 2 or 3 220uF as planned will need to go with 5 to 10 100uF capacitors in parallel.
The inrush current will be limited with AMETHERM - SL22 40005 (probably 2 of them) or EPCOS - B59201J0140B010
Instead of choke and transil will use stock Surge Protector Power Strip which has them inside already and will also protect other equipment later.

Thank You, but I hope not to need more as unsoldering from old boards will be a nightmare.

That's my intention. As I said I have a working string on 24V DC (in fact 26V). The key here is the use of the CMQ - immediately after plugging it in the outlet the string self-tunes to ~1.5A. When latter the miner is started on the RPI, it configures the chips with 52 bits clock (~190MHz) during the detection phase, which is later increased to 54 bits (~215MHz) or 55 bits (~230MHz). This is enough as startup procedure at the moment and hopefully will be enough for a longer strings to. Just in case it's not, there is plan B - the miner (with my own changes and web interface) allows changing the bits for each/any chip at runtime, so a simple external/web script can do that very easy.

Bitfury stuff loves to run in strings. Remember they built 48V single-wide strings for their own DCs and apparently got along well enough.

Are you running this off a single phase 230v line? Id love to see this work, but hate to say that running a 300-400 line string would surely end in disaster. There is a reason why most ASIC boards have very short strings, and some multiple strings in parallel. Its hard enough to provide clean power to the asics with a clean 12v DC power input...trying to do that with an a single phase AC line on a 400 line string is insane lol. The ONLY way this would be possible is if you have some very sophisticated startup and hash phase loop control down to each asic (I guess this could be implemented fairly straighfoward by controlling the PLL clock for each chip seperatly, but that would still be a coding nightmare, and not sure what kind of device you would need to have to control 400 I/Os in sync   .

Hit me up if you ever need more chips. I have hundreds of the old bitfuy H cards

STEP 3 - Filtering capacitors
For a stable operation usually several mF capacitor would be required for such setup, but because of chip specifics we can go with much smaller capacitor (values in uF):

	205V AC	220V AC	230V AC	235V AC	265V AC
392 chips	152.37	101.94	85.18	79.1	57.65
406 chips	198.58	117.39	94.44	86.53	60.23
420 chips	295.24	140.56	107.19	96.47	63.43
434 chips	618.47	178.67	125.6	110.27	67.41
448 chips	X	252.12	154.17	130.45	72.42

And the same calculations with 2A current

	205V AC	220V AC	230V AC	235V AC	265V AC
392 chips	181.3	113.02	90.34	82.1	53.07
406 chips	244.72	134.8	103.74	93.02	57.42
420 chips	376.39	166.97	121.8	107.28	62.56
434 chips	814.74	219.32	147.47	126.72	68.7
448 chips	X	319.48	186.86	154.74	76.18

My expectation was for 600-700uF and as it turns out it's close enough for the worst case (434 chips @ 205V), but if we can accept miner resets when the voltage drops below 220V stock 330uF should suffice for 448 chips and we can even go with just 120uF for 392 chips
There is no way to run 448 chips at lowest voltage ( 205V ) except if we reduce the current below the optimal by setting clock bits below 50. For lower J/GH that's an option, but my broads are designed around the optimal power point (1.8A @ 0.8V) and even that will not help, because the CMQ will try to bring them there (~1.5A actually).

Just to make it clear, because few people have PMed me with similar questions ...
This project will not bring back to live your old Bitfury gear nor it will make the 55nm chips profitable again.
The production cost is over 1BTC while 1TH miner with free electricity will make 0.05 say 0.1BTC for it's entire live.
I put money in this project for fun (as a hobby), not for profit!

I have enough chips for the initial tests, so there is no need of more (for now). For the PFC tests i may use some of my old (damaged) boards if nothing catastrophic happens with the rest of the boards.

Not 230V DC but 325V DC = SQRT(2) * 230V ~= 1.4 * 230V

I have some PCBs printed for the 55nm and got some chips for free. Just the assembly will cost ~0.5 BTC and will need some other parts too while this is a hobby project and can't afford to spend on recent chips.

With the 16nm chips it will be definitely possible too (if this one works), but it will be much more difficult - more stable voltage will be required (i.e. setup with PFC, because the CMQ was removed) there should be dedicated SPI/controller for each 50-100 chips, while the setup will take ~870 of them and ~110 of their levelshifters add to that ~20 controllers and you will get a 50-60TH monster eating ~4kWh, which a single 16A circuit won't handle

Interesting. Why not try with recent chips?

am i missing something - how are you turning your 230V AC into 230V DC for the chips?

Upon reflection, might try getting in touch with MegaBigPower and see if they still have their old 55nm Bitfury gear around and are willing to sell it.

Looking at this again ... the PFC might be really better for the efficiency and those 10W-20W wasted in the PFC will be compensated by not having the performance drop caused otherwise.

PFC will need 504 chips (next step 9 panels) and lower (~240kHz) max SPI, but as it turns out it should still be enough for proper communication.

I will be few chips short for 9 panels and there will be no chips left for replacements after the fireworks, but will definitely try the PFC setup if enough chips survive the first tests

STEP 2 - determine the number of chips limit for the string based on SPI speed

Each chip has 4ns propagation delay of the signal, which places limit on the number of chips one can access with a single SPI (in a single string)

For 448 chips the maximum SPI speed possible is ~279kHz - let's use 200kHz (may need to be lowered further down to 100kHz) for noise immunity.

Expected GH per chip (they are Rev2) is calculated as MHz * 0.864 / 65 and optimal 235MHz (1.8A @ 0.81V with 392 chips) = 3.1GH with total of 1.2TH @ ~600W
For 448 chips expecting 1.7A @ 0.74V and ~180MHz which is 2.4GH or total 1TH @ ~560W

Each communication is ~100 bytes, so 2000 at 200kHz and 1000 at 100kHz. In all cases we will have at least 2 communications per second per chip, which should be enough not to miss shares and to send the next job to the chip in time, as it will take ~1.1sec per job with 3.1GH.

The real speed will be lower (because of HW errors and speed drop with the voltage) and the power used a bit more (because of the required fan and the current limiter + some other components), but 0.6J/GH seems possible target at max possible clock bits for that voltage.
It may go further down with lower clocks with expected minimum of 0.45J/GH for ~500GH, which is impressive for such old chip, but TBD ...

Yep, that's what I was talking about. The 55nm chips have some very neat specs that allow running on mostly bare chips in long strings.

The negative temperature coefficient is accounted for in my design using another peculiarity of the chips - the built in current mirror (CMQ). As I said the voltage is almost perfectly (blaming component tolerances mostly) balanced and the CMQ response is few nanoseconds

Sad but true. My next post will be about that, but so far it's not looking too bad.
Will use RPI (initialy) mostly because I have a working miner with it and it will be easier to modify the code at runtime.
Level shifting is required only to the first chip 3V3 <-> 1V8 (actually ~1V6 = doubled core voltage). And (from my next post) the SPI speed should be so low that even a simple discreet elements LS should be fast enough, while SN74AVC4T774 will be used.

But in this case the load varies with the voltage too, so they balance each other for free.
One farad at 400V ?!? Don't want to sell a kidney, so no, but yes - the filtering capacitor will be the most demanding part (will post about that in STEP 3)

but now ...

The old 55nm chips were designed to string without an external level shifter. Maybe some passives between chips, but nothing serious. Take a look at the old OneString boards, they're pretty barebones.