Now we're looking at the code.
This wasn't the exact file I had but maybe something has changed I don't know, it's close enough in the places that matter anyways.
Anyways for the crux of my argument, take lines 124 through 142 which consist of the bulk of the random number generator.
These are currently implemented as defines.
That isn't a random number generator. You're looking at macros for the SHA256 rounds. Just stop, and go read the scrypt whitepaper. Immediately, if not sooner.. I'm not trying to be rude, it's just that an immediate read of the scrypt whitepaper will be better use of your time at this point.
*embarrassed*
That's actually a good catch and frankly something I had not seen before but should have.
It would have been a costly mistake to proceed on that and while I can see now it's Round not Rand for RND, I openly admit I did not see that before and this was a critical thinking error.
Thank you both for showing me my mistake.
It completely breaks my premise.
There is no need to raise further funds for this. These two have shown me a critical flaw in the plan which would have been to isolate the RND function off onto it's own core.
I'm really glad the original author came on and explained this because to me it wasn't clear and in the absence of anything resembling a comment in the source code, I find this information extremely valuable.
So here is what we've learned.
#1 I need to review closer to make sure the code is doing what I think it's doing when working with someone else code, especially when that code has no comments and all I have to go on is a whitepaper.
#2 I did in fact see the RND define as a hand written psuedo-random generator. It is not one, and had my brain been in anyway functional I should have caught that before making an announcement of this type. In my mind it's still a candidate for optimization, but that's probably just me being stubborn.
#3 Not that it's advisable but...
There are several dev boards and OpenCL FPGAs out there on the market.
It should in theory be possible to modify the OpenCL miner to run on one of these FPGAs.
The Altera Stratix V is at the high end of these and I did burn one out trying.
That should be enough of a start, however I do plan to keep chasing this dog until it barks. I'm no longer asking for contributions of any kind, I've gotten the information I needed. I really appreciate everyone's patience on this.
Anyone who wishes a refund is entitled to it.