Topic: Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards - page 48. (Read 119429 times)

Amazon EC2 FTW!

New plot.  Two rings, 161mhz.  As you can see I'm getting closer to being able to cram that third ring in there.

They're spot instances; it's about $7/hr to run 25 of them & they're started/stopped on demand.
Definitely worth it in terms of build time reduction.

-rph

Are you seriously running all those instances? I hope not for too long...

heh, I'm still working on that..



-rph

So, 320MH/s is possible... Nice...

Yeesh, finally figured out how to force the router to do what I want.  Over 160mhz now and the next steps should be straightforward.

This was ridiculous.  I seriously think I've spent as much time on this one problem as all the other HDL work put together.  Nothing is worse than dev tools that think they're smarter than the human.

Artforz, do you have any recommendations for an ATX power supply to be used as the 12V source for twelve YV09T60-0G's?  Only linear regulators on the 5V line and no use of 3V3.

A single 850W supply will power my entire cluster, so I'm willing to shell out bucks for quality if it's worth it.  Unfortunately I know very little about the analog/power-supply end of this stuff.  Your wisdom would be welcome here.

So don't use the 3V3; regulate it yourself from the 5V line.  The FPGAs draw negligible current from the 3V3 so you can just use some cheap+simple linear regulator.

Those four-pin molex connectors need to die.  These are hand-solderable even by klutzes like me.  Doesn't look like you can get just the power connector alone, though, so you wind up with an unconnected SATA data port.  Dremel it off if you like.

One way to solve that is to have each FPGA drive the JTAG inputs of the next one; this way every signal has a fanout of 1 (credit goes to rph for this idea).

Well... yeah. If you happen to find a ATX psu that's just barely within spec, it's outside of the nominal supply range of a S6. By 15mV.
ATX spec also requires a 1A min load on each of 3.3V, 5V and 12V, so below that regulation can be bad (a real problem with group-regulated PSU designs).
With modern high-efficiency psus generating their 5V and 3.3V with step-downs that issue seems to have pretty much vanished, some mV ripple at a few 100kHz+harmonics, nice and well behaved load step response even down to 0 load.
As for seeing nasties on a 'scope ... are you measuring on a unloaded/unterminated line? Try with 10uF || 330R, or you'll be mostly measuring weakly coupled interference, transmission line effects/line resonating with your probe capacitance.
But then I've only closely looked at 2 zippy and 2 superflower units, all of em 80+ gold or better and all of them good enough that I decided the added cost+complexity of a 3.3V step-down for each 8*LX150 board wasn't worth it.
Had more issues with vccint droop, on my boards a 3-phase DC/DC was at one end of a 190x85mm board... close to a 50mV drop to the furthest pair of LX150s. Salvaged by adjusting the converter up to 1230mV and adding lots of jumpers. rev1.1 moved the converter to the center of the board and rev2 changed the board geometry completely (2 rows of 4 instead of 4 rows of 2).

It probably is a good idea to use a high quality supply. My Corsair (bottom end) CX600 has a pic like this according to JohnnyGuru reviews. (3.3V, light load). Their high end ones are surely even better.



1% of 3.3V would be 33mV.

This design has light weight, low speed I/O and from what I read the 3.3V is just for the I/O buffers.

I'm astounded that it's stable enough - especially under light load..  I'm happy to hear it works, I'm just shocked.  Most ATX Supplies I've looked at with a scope have been a mess - especially at lighter loads where they have a harder time regulating.

Even the ATX Specification doesn't suggest that it would be good enough.. The tolerance for 3.3V is +/- 5% (3.135 - 3.465) and the top and bottom end of that range are both outside of the VCCAUX spec of the spartan 6 ( http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf ).

Like I say - I'm happy it works... Just surprised it does..

Enigma

I'm astounded! I knew you were way ahead but didn't think it was that many.

My goal with above is to keep each unit costing $200 or less. Right now at qty 1 it's $190 (plus any shipping). At qty 25 it's $185, all sourced from Digikey and Mouser, but if I get connectors locally here in Asia then that knocks off another $7. I've got samples from 4uConn before but can't see buying the moq of 1000 each.

I'm not planning to resell these but I may sell pcb boards or kits without fpga if it actually works. Just for hardcore toaster hackers. I don't have the money nor infrastructure to get into buying & selling fpgas. Any design/code I'll most likely release as open source.

Heh, I feel even darker building a new GPU based rig right now.
Oh well, my BFL pre-order is in - if they deliver, I shall be advancing into the new millennium! 

....  I feel like I am in the dark ages running all these gpu's....

My current plan is to put a Molex MicroFit 3mm 6 pin header on board supplying 3.3V, 5V, 12V. I thought about a Sata 15pin but they're hard to find and also users might screw up by attaching one with only 5V+12V. Seems to be common to leave off the 3.3V. so bad idea. But these are small and quite robust.

Then use a Fairchild FAN2108 to drop 12V to 1.2V. The specs indicate close to 90-95% efficiency for mid-high loads which is much better than the AOZ1025 under full load. It needs 5V for bias voltage so running off a 12V adapter isn't ideal. But everyone has a ATX PSU around anyway as they've been mining w/GPUs til now This all allows me to bring the board size down to minimum which saves a lot of money.

On the board the 3.3V and 1.2V are on the bottom and come in from one side where PSU is located. The GND is poured over remainder and interlocks with thick traces into 1.2V grid. Then the top layer has just a small number of signals from edge of FPGA to connectors, less than 1cm. Vias and traces just barely doable with low-cost board fab. This is all highly unusual for FPGA board but remember here we only a few small low freq signals near the board edge. Ultra minimal design. I've already drawn on paper but need to get into computer.

Each board has a 6 pin right angle header bottom center edge, and 6 pin right receptacles at other 3 sides center edge. So boards can sit next to each other and 3 neighbors connect to each master. They continue as such relaying 4 lines for each. No long signal paths, only 1-2 cm,  for a variant of SPI between boards. Each board has a simple control register and 4 way multiplexer. Control byte sets whether talking to this board or bypassing to 1 of 3 neighbors, or local data, temperature and CLKGEN sampling.

Large heatsink on board but no fan as they will be too close and just pollute each other. Large fans above force air thru and out all units. LCN75 sensor under each FPGA allows monitoring temperature.

The one master-master unit will connect by short cable to GPIO on my Core2Duo mini-itx board. Later I hope this will connect to a R-Pi instead as that's cheaper, smaller and way cool. Hopefully will write new kernel for cgminer and run that on R-Pi but unsure about that for now.

... says who? According to spec it should work fine, and reality over here agrees. 54 S6s happily running with vccio and vccaux fed from atx3.3.

ATX 3.3V is not well enough regulated for supply directly into an FPGA.  Don't try it.  Regulate it yourself from ATX 5 or ATX 12

Enigma