I suspect the situation is a LOT more complex than you believe, due to interaction of multiple compute units trying to access memory at the same time, wait state timings on the actual memory, etc.
GDDR5 RAS/CAS timings has nothing to do with the bandwidth of the data xfer.
Of course it does...if a memory controller has to wait more clock cycles before it can read or write to a memory bank, its effective I/O bandwidth is reduced.
Try reading a GDDR5 datasheet. Every mfr supports at least 8 concurrent open pages. 2 bursts (4 clocks) from the same page are required to max the I/O bandwidth due to the 1:1 command:burst ratio. In the context of the Hawaii cards with a memory clock of 1250 or 1300Mhz, faster page activation times than stock make no difference in the data xfer rate.
When the time for 16 burst xfers is less than the time to activate a page, only then will page activate timing impact bandwidth for the minimum 64-byte xfers. You'll run into that issue with an Rx 470 at 1750Mhz, but not on a R9 290 at 1250.
I have read almost the entire Hynix GDDR5 data sheet, and am probably one of only a handful of people that have decoded the entire memory strap region of the ATOM bios. Of course timings wouldnt matter for slower clocks...but no one on these forums run their memory clocks at 1250 or 1750
One of the few except for people like me that have mapped out the ENTIRE BIOS with some little tools like atomworks---
