Because if you must communicate between your PC and your FPGA, this might slow it down quite a lot.
As long as the FPGA performs millions of hashes for each "call" (host sents work to FPGA), host<->FPGA communication cost is small.
Topic: An estimate of fpga performance - page 6. (Read 51502 times)
As long as the FPGA performs millions of hashes for each "call" (host sents work to FPGA), host<->FPGA communication cost is small.
How does this compare to a GPU?
Ok but in order to mine don't you need a full VHDL implementation of the miner code ?
Because if you must communicate between your PC and your FPGA, this might slow it down quite a lot.
Also I don't understand : have you just done simulations or have you tried on the actual device ?
Because if you must communicate between your PC and your FPGA, this might slow it down quite a lot.
Also I don't understand : have you just done simulations or have you tried on the actual device ?
Hello!
I converted the sha256 available in opencores.org into vhdl, just to see what to expect.
I got an xc3s500E about 1/3 full on the logic gates, so with a shoe horn one could maybe fit 3 cores into one of these. That does not include the communications with the host, nor the "less than" compare if the result is below the current threshhold.
(I used an antique ISE (8.something) so maybe newer versions will compute better).
Assuming a maximum of 300 MHz and about 80 cycles to read in, process and output the result (8 + 64 +
You'd get 3*300/80 ~= 11 Mhash/s
This device can be had on a nice DIP socket (GOP modules) at about 60 EUR.
If you want to run this simulation (only tried on Linus), you need ghdl and gtkwave packages (and probably some more stuff that I forgot).
The tar in the attachement contains the synthable file sha256.vhd and the test_sha256.vhd and a simple Makefile.
I converted the sha256 available in opencores.org into vhdl, just to see what to expect.
I got an xc3s500E about 1/3 full on the logic gates, so with a shoe horn one could maybe fit 3 cores into one of these. That does not include the communications with the host, nor the "less than" compare if the result is below the current threshhold.
(I used an antique ISE (8.something) so maybe newer versions will compute better).
Assuming a maximum of 300 MHz and about 80 cycles to read in, process and output the result (8 + 64 +
You'd get 3*300/80 ~= 11 Mhash/s
This device can be had on a nice DIP socket (GOP modules) at about 60 EUR.
If you want to run this simulation (only tried on Linus), you need ghdl and gtkwave packages (and probably some more stuff that I forgot).
The tar in the attachement contains the synthable file sha256.vhd and the test_sha256.vhd and a simple Makefile.
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