I am sure burnin knows the shortcomings of his own design.
It should be easy for him to make the improvements.
He's one busy guy and maybe not interested.
Topic: Avalon 55nm ASIC open source design contest - page 2. (Read 3567 times)
I would think that burnin could submit a slightly modified version of his design and win quit easily.
The Bitburner XX design is a good one and it's all ready done.
The Bitburner XX design is a good one and it's all ready done.
Burnin has done an outstanding job, and it would be very satisfying if he won the chips.
However, there must be at least 3 ways that his, or anyone's, design concept could be improved.
Thread is for "Pro-Avalon" only 
I would think that burnin could submit a slightly modified version of his design and win quit easily.
The Bitburner XX design is a good one and it's all ready done.
The Bitburner XX design is a good one and it's all ready done.
Avalon has announced a design contest.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
Even with a 5,000 x 55nm chip prize I think Avalon will have issues attracting participants. Why? Because they are not honorable business people. They have been negligent and dishonest. If I could design PCB, I might do this...but I am looking this from a 3rd person perspective.
I have applied to be a participant, and I have been accepted. This puts me into a conflict of interest situation if I trash talk Avalon and actively discourage other entrants. So again, please, stay on topic in this thread.
Avalon has announced a design contest.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
Even with a 5,000 x 55nm chip prize I think Avalon will have issues attracting participants. Why? Because they are not honorable business people. They have been negligent and dishonest. If I could design PCB, I might do this...but I am looking this from a 3rd person perspective.
Avalon has announced a design contest.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
The timeline is very compressed. I thought this would be a good place to gather any thoughts that potential customers have for design elements, and any comments that other designers / contestants have to make.
The break-even time matters as well. More cool features cost design delay and component cost. A URL for a pre-populated calculator might help the designers decide whether to push an adequate design out now, or spend more time cutting costs.
The only design element that is fixed is the 55 nm Avalon ASIC chip. Everything else is designer's discretion.
This is a self-moderated thread. Please stay civil and on topic.
The chip is specified as 1 GH/s @ 2.05 W with 128 Hash units on the chip.
I have not noticed any pricing information. You might want to submit a URL for a profit calculator that will suggest the time to break even that you consider realistic.
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