Any chance you will offer cooling installation as an option?
ps-I doubt it but wonder if anyone will offer to provide a hosting service for boards like these...
Topic: BFL ASIC mining board project - page 12. (Read 36538 times)
@daemonfox, once everything is ready to take board payments I'll collect both the last half of the ASIC money as well as the board money (unless you just want the ASICs). No point in doing all that twice, and I don't want to take anyone's money until we've demonstrated a working product.
@jelin, I'm sorry you feel that way. We'll try and get the price down as much as possible, but even if it is $300 that is still competitive per GH/s with other board assembly services our there.
@erk, exactly how we implement 8 chips on a board is still up in the air. I would like to put all 8 under a large heatsink simply because it will keep the size down, but we'll have to see how well the chips respond. Getting two LGA1156 heatsinks on a 100mm x 150mm will be impossible.
@keefe, you could remove them, but you would need to reball the ASICs before resoldering them. I don't think it's worth the risk.
@jelin, I'm sorry you feel that way. We'll try and get the price down as much as possible, but even if it is $300 that is still competitive per GH/s with other board assembly services our there.
@erk, exactly how we implement 8 chips on a board is still up in the air. I would like to put all 8 under a large heatsink simply because it will keep the size down, but we'll have to see how well the chips respond. Getting two LGA1156 heatsinks on a 100mm x 150mm will be impossible.
@keefe, you could remove them, but you would need to reball the ASICs before resoldering them. I don't think it's worth the risk.
Watching
Would it be feasible to remove BFL ASIC chips from BFL units and put them on your boards? Your board design may end up being more desirable than BFL's, especially for the clock/voltage control.
Without special reworking equipment, you would most likely destroy them.
I'd call that feasible but not without risk and cost. Kinda like if you wanna swap hearts with your identical twin.
Would it be feasible to remove BFL ASIC chips from BFL units and put them on your boards? Your board design may end up being more desirable than BFL's, especially for the clock/voltage control.
I like the idea of the 4 chip board, that keeps the heat down to similar levels that CPU coolers were designed for.
great work here!
Good but price is very high
I think better price will be at 250 dollars or 200 dollars
I think better price will be at 250 dollars or 200 dollars
Watching
Excellent update MrTeal.
Just one thing, that I hope I did not miss somehwere else... when is the time frame for the remainder of the 50% BTC for those who participated in your chip buy. I have yet to see or hear when I am supposed to send the remainder of my half for the chips. Or is that just incorporated into the final payment you need to assemble and ship a working unit?
Just one thing, that I hope I did not miss somehwere else... when is the time frame for the remainder of the 50% BTC for those who participated in your chip buy. I have yet to see or hear when I am supposed to send the remainder of my half for the chips. Or is that just incorporated into the final payment you need to assemble and ship a working unit?
Keeping an eye on this still, hope I'm not too late by the time my liquidity situation eases.
MrTeal, this looks great! Keep up the excellent work.
If you have a list of users looking to have units assembled by you (self-supplied chips), please add me to it.
If you have a list of users looking to have units assembled by you (self-supplied chips), please add me to it.
Looks promising. Good luck.
hm... interesting.
good luck
good luck
I'm branching this off from the old group buy thread, as that has a lot of posts that just aren't that applicable to the actual board design.
Project Description
This project is being developed by Mr Teal and Chip Geek, with the purpose to provide a high performance mining platform for the Butterfly Labs ASICs. By leveraging existing infrastructure in the PC space, the plan is to provide the chips with high levels of thermal and power headroom without spiraling cost out of control.
Once the design is proven, orders for the boards will begin. Chips can either be ordered through myself, or you can order chips and have them resent to us to have them populated onto miners.
Product Description
The final design is still under development, but it will broadly incorporate the following features.
Test Board Description
A test board has been designed to test the BFL ASICs, and is slated to be done manufacture July 18th. It incorporates a 3 phase VRM, many extra test and debug features, and space for 4 or 1 ASIC.
The primary aspects that testing will focus on will be:
1. Validating the design and the power supply, testing the current limits and temperature rises.
2. Ensure the microcontroller maintains safe control of voltage with no unexpected excursions.
3. Test the microcontroller, verify the code base and communication with peripherals.
4. Test ASIC communication, and hashing.
5. Characterize the BFL chip, examining the chaining of Done signals, whether the onboard temperature diode works, and external clocking.
6. Test board chaining using the Zlink (chaining) interface
Project Status
Done:
June 1st - BFL announces chip sales, basic design ideas begin
June 16th - Group buy initiated
June 22nd - Group buy order placed
July 3rd - Sample chips shipped
July 12th - Samples received, final PCB review
July 14th - Test PCB sent for manufacture
July 18th - Estimated PCB ship date
Upcoming Estimates:
Week of July 22th to 28th - Begin building and testing of PCBs
Week of July 29th to August 4th - Continue testing, incorporate results into the production version
Week of August 5th to 11th - Begin taking orders for PCB sales, send out a small quantity of production boards for manufacture, finalize assembly information
Week of August 12th to 18th - Receive and build production test boards. Test, and if necessary, modify and respin board
Week of August 19th and beyond - Prepare for production, further testing and rework if needed, extra lead time. Final PCBs produced. Components ordered and stocked.
Mid September - Chips arrive and head to assembly
Feel free to ask any questions, and I will keep everyone updated as milestones are retired and the project goes along.
Project Description
This project is being developed by Mr Teal and Chip Geek, with the purpose to provide a high performance mining platform for the Butterfly Labs ASICs. By leveraging existing infrastructure in the PC space, the plan is to provide the chips with high levels of thermal and power headroom without spiraling cost out of control.
Once the design is proven, orders for the boards will begin. Chips can either be ordered through myself, or you can order chips and have them resent to us to have them populated onto miners.
Product Description
The final design is still under development, but it will broadly incorporate the following features.
- 8 chips - nominally 30GH/s, extra hashrate depends on grade
- Dynamic clock and voltage control
- USB control, 12V 6pin PCIe for power
- Hole spacing designed to allow many standard CPU coolers to cover the ASICs
- 3 or 4 phase VRM capable of providing well excess of 100A to the ASICs
- Each module will be designed to be run stand alone, or chained together through a single USB port
- Preliminary size ~ 100mm x 150mm, standard 3.5" HDD footprint
Test Board Description
A test board has been designed to test the BFL ASICs, and is slated to be done manufacture July 18th. It incorporates a 3 phase VRM, many extra test and debug features, and space for 4 or 1 ASIC.
The primary aspects that testing will focus on will be:
1. Validating the design and the power supply, testing the current limits and temperature rises.
2. Ensure the microcontroller maintains safe control of voltage with no unexpected excursions.
3. Test the microcontroller, verify the code base and communication with peripherals.
4. Test ASIC communication, and hashing.
5. Characterize the BFL chip, examining the chaining of Done signals, whether the onboard temperature diode works, and external clocking.
6. Test board chaining using the Zlink (chaining) interface
Project Status
Done:
June 1st - BFL announces chip sales, basic design ideas begin
June 16th - Group buy initiated
June 22nd - Group buy order placed
July 3rd - Sample chips shipped
July 12th - Samples received, final PCB review
July 14th - Test PCB sent for manufacture
July 18th - Estimated PCB ship date
Upcoming Estimates:
Week of July 22th to 28th - Begin building and testing of PCBs
Week of July 29th to August 4th - Continue testing, incorporate results into the production version
Week of August 5th to 11th - Begin taking orders for PCB sales, send out a small quantity of production boards for manufacture, finalize assembly information
Week of August 12th to 18th - Receive and build production test boards. Test, and if necessary, modify and respin board
Week of August 19th and beyond - Prepare for production, further testing and rework if needed, extra lead time. Final PCBs produced. Components ordered and stocked.
Mid September - Chips arrive and head to assembly
Feel free to ask any questions, and I will keep everyone updated as milestones are retired and the project goes along.
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