Topic: BFL Reliable? - page 6. (Read 6717 times)

Here is the currently estimated timeline, and while this is subject to change of course, it's pretty solid at this time. Completed items are crossed off:

    Week of January 13th
        Travel to packaging facility for final prep and walkthrough - Complete
        Confirm travel plans and trip details with lead ASIC engineer for trip to fab - Complete

    Week of January 20th
        Final assembly facility prep - In progress

    Week of January 26th
        Leave for fab/bumping facility at the end of the week
        KC facility starts assembly process of units to drop PCB into Units being prepped!

    Week of February 3rd
        Final chips roll off the line
        Arrive at Bumping facility
        Chips Bumped
        Arrive California for Packaging (May spill into following week)
        Chips packaged

    Week of February 10th
        Packaged chips sent to assembly house
        Assembled PCB is set for final testing and MCU programming
        Notify users to start sending their FPGA units or BTC for trade in participants
        Bulk assembled PCBs arrive in KC, we start dropping PCBs into waiting units
        Boxing/labeling for shipment
        We implement the 1/3 shipping plan en mass
            1/3 of our assembled units will go to new orders in FIFO
            1/3 of our assembled units will go to upgrade orders
            1/3 will be randomly selected from both groups
        We descend upon the Post Office like horde of angry locust. DHL, UPS and FedEx send trucks.