Topic: BFL SC Die Guestimation/Speculation - page 2. (Read 4119 times)

If Altera HardCopy is used it will be on 28nm, with a maximum of 11.5M gates, or a maximum hash rate of 12.35 GH/s at 1 GHz, but these run at 400-700 MHz typically.

If this really is the case, the power usage will not be much less than the corresponding ASIC.  Altera themselves state, "Average of 50% performance improvement over corresponding FPGA, average of 40% less power consumption compared to corresponding FPGA."  Thus, from a hash/s/w standpoint, the ASIC would be about 200% greater than the corresponding FPGA.  A by-hand design like that of CAST's ASIC would be the only ASIC able to really deliver the kind of power consumption BFL has been hinting at.

1. jalapeno will not be only USB powered
2. FPGA's use 45nm (or lower) technology and hardcopies of that also

=> they will probably use an altera hardcopy as the current models are based on altera FPGAs.

But the power problem remains. The hardcopies are apparently not more power efficient. This would question the idea of providing a Mini Rig SC as it would consume 40 x 1kW [if it would be based on FPGAs ... and if hardcopies consume as much power].

Okay, I read some notes on this here and it makes sense.  Basically, [for people reading about this too], the toggle rate is the number of transistors changing state per clock cycle designated a.

The net toggle rate n is such that
n = f × t
where f is the clock frequency and t is the ratio of transistors switching state per clock cycle.  For a SHA256 ASIC, we would assume this to be 98% or 0.98, whereas for a typical CPU or GPU this would be much less as SHA256 hashing would not require state changes for transistors in components not used, such as the FPU.

The total power consumption p of the ASIC is then
p = n × transistor dissipation factor (constant for the same process, e.g. 130 nm, but becomes a smaller constant as the fabrication shrinks)
because electricity is wasted (dissipated) with every state transition for the transistor.

Thus, as tytus stated, this chip hashing at full speed would likely require some 2x-10x more power, making the TDP 120-600w.  However, if the process were 28-45nm, a TDP close to that quoted by BFL may be possible, but it seems unlikely they have access to such an advanced fabrication method (which would require tens of millions of dollars in investment to get off the ground, most likely).

See also: http://cis.poly.edu/cs2214rvs/powers03.htm

So, the power claims by BFL are actually dubious... which is not surprising, given the 6x difference in power for their BFL single unit between quoted and actual.  This is all pretty suspicious.  If BFL really wanted to keep the user informed, they could at least give the process they're working on, the transistor count, fab location, etc like a real company that does chip fab, but so far all they're giving us is a place to send money to them and a hashing speed.

Further, BFL may risk patent infringement if they use published technical methods for the ASIC circuit designs.  But since BFL has said mostly nothing about the way it works, who knows?

edit: 10 BTC says they're just reselling CAST's ASICs for SHA256



So there you go, it's probably on TSMC 90 nm.  If this is the case then the 2.5 W of draw for the jalapeno is probably not true at all.

That would be with the end values of what he considers possible. But assume his values 56.9GH/s and ~60W it is 3.7W. Still high. Maybe, they have two USB cables, or maybe, sicne it's referred to as a "coffee warmer", they intended to overdrive it to make more heat? ;-)

||bit

Assuming your data is correct, one Jalapeno (3.5GH/s) would need 5.25 Watt.

But a USB port provides only 2.5 Watt.

Hmmm ...

A CPU has much smaller toggle rate [will use much less power than the Hashing chip ... maybe even 10 time less]. Getting 1GH on 130nm is probably also not easy.

sounds good to me.

I'm not an electrical engineer, so probably someone who is will shit all over this.  Anyway.

I think these chips are small and probably on 90-130 nm technology.

SHA256 hashing requires about 13,500 logic gates per circuit or 27,000 transistors.  An AMD K8 130 nm CPU has about 106M transistors in 100mm^2 with a TDP of 60W, so we could fit about 3926 SHA256 hashing circuits on one of these ASIC dies.  These hashing units run at 65 cycles per hash; we would expect from an immature 130 nm process for the ASIC that clock rates of 1 GHz would be achievable.  This would mean 14.5 MH/s per hashing circuit or 56.9 GH/s per 100mm^2 die with a 60W power consumption.

How does that compare to what has been given to us by BFL?  The BFL single, which is assumed to be a single die, is rated at 40GH/s.  With the above ignoring crucial things like transistors for I/O, it does indeed seem possible that the BFL single can provide 40GH/s at 60W on a 130 nm process.