BFL is making it look like the chips working are a done deal. To give the aura that things will be done soon. All the while updating people with details on what....well what they actually don't know yet "for sure"...whether the chips actually work at the speed they originally intended.
Josh mentioned at the beginning of the weekend that the chips were about to go through full speed tests a few days ago after they ran a low speed functionality test. Then he turns around at the end of the weekend and reveals that this can't be done without the full packaging.
You can tell they are cowboys. Cowboys that are clearly disconnected from the process or the innate knowledge of what is necessarily possible by the professionals making the ASIC design.
So far, they sacrificed 1,000 chips (a full wafer) for functionality tests. Seemingly without a reason (they are cowboys remember?). Had they actually known that the full speed tests could not be done without proper packaging, they would probably have not scarified a full wafer. When they did sacrifice a full wafer, they seemed to be unaware that full speed tests would not be "do-able".
Next, they have begun finalizing the next batch of 6 wafers before they actually know what will actually happen when all 16 cores hash at full speed. (magic smoke?)
So if there is anything wrong, the second batch will likely suffer from it as well.
Topic: BFL - Update 3/4 - page 3. (Read 5060 times)
You know what I find interesting?
The fact that in this ASIC project they are using valuable time to test the chips and at the same time convince customer(s) they actually work.
This is what should normally take a few weeks as pointed out by a few hardware folks on this forum. This necessary testing process is being compressed into a few days in an "Ad-Hoc" manner.
What is even more interesting, is that some false impressions are being beamed out.
For example, BFL customers are being comforted with the illusion that their chips will ship soon "for certain". But...they are still running the chips through "functional tests". NOT full throttle performance evaluation(s) mind you, no, just basic low speed functionality tests.)
So in essence BFL is taking a calculated risk for the sake of speed. What normally would have been done in a back room somewhere (away from prying eyes) for a few weeks is actually being done in open view.
That doesn't bother me much as a spectator.
What really does bother me, is that two mixed impressions are being given out. The first false implied impression that the chips work and will ship soon. (they don't know this yet, but thats why they are testing it.)
The second false impression is that the chips are just undergoing a "little testing" to confirm things are in working order. That isn't the case. The testing going on is whether the design actually functionally works, whether it meets (performance/electrical) specs and finally whether the chips ultimately are worth while.
Anyone with a semblance of understanding would read these updates and realize that alot of praying is going on as they rush through each step.
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Keep this in the back of your mind when you read what is being disseminated or at the very least when you ask the next question. Because someone who has a false impression would be disappointed if the chips break at stock speed.
While someone who is an engineer or a semi-conductor designer knows this is simply a reality of the "testing phase" of a design.
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The fact that in this ASIC project they are using valuable time to test the chips and at the same time convince customer(s) they actually work.
This is what should normally take a few weeks as pointed out by a few hardware folks on this forum. This necessary testing process is being compressed into a few days in an "Ad-Hoc" manner.
What is even more interesting, is that some false impressions are being beamed out.
For example, BFL customers are being comforted with the illusion that their chips will ship soon "for certain". But...they are still running the chips through "functional tests". NOT full throttle performance evaluation(s) mind you, no, just basic low speed functionality tests.)
So in essence BFL is taking a calculated risk for the sake of speed. What normally would have been done in a back room somewhere (away from prying eyes) for a few weeks is actually being done in open view.
That doesn't bother me much as a spectator.
What really does bother me, is that two mixed impressions are being given out. The first false implied impression that the chips work and will ship soon. (they don't know this yet, but thats why they are testing it.)
The second false impression is that the chips are just undergoing a "little testing" to confirm things are in working order. That isn't the case. The testing going on is whether the design actually functionally works, whether it meets (performance/electrical) specs and finally whether the chips ultimately are worth while.
Anyone with a semblance of understanding would read these updates and realize that alot of praying is going on as they rush through each step.
--------------------
Keep this in the back of your mind when you read what is being disseminated or at the very least when you ask the next question. Because someone who has a false impression would be disappointed if the chips break at stock speed.
While someone who is an engineer or a semi-conductor designer knows this is simply a reality of the "testing phase" of a design.
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28th of Feb they were going to be testing to 500Mhz the following day, ie the spec they were designed to work at. 3-4 days later still only tested at 350Mhz and some mumblings about certain non-specific issues.
Sounds like the same old delaying tactic deployed for months on end now. Can't see BFL actually surviving much longer.
If they don't deliver something soon they WILL go bust. Avalon aren't far behind following suit with their BS stunt using #2 to fund #1 orders.
Think i'm gonna place a bet on BFL not delivering this month, and take the winnings on an up.
Sounds like the same old delaying tactic deployed for months on end now. Can't see BFL actually surviving much longer.
If they don't deliver something soon they WILL go bust. Avalon aren't far behind following suit with their BS stunt using #2 to fund #1 orders.
Think i'm gonna place a bet on BFL not delivering this month, and take the winnings on an up.
Can't wait for tomorrow's thread 3/5 .... then maybe 3/6??? yes?? PLEASE?!?!?!
For anyone who doesn't want to browse their forums:
https://forums.butterflylabs.com/announcements/692-bfl-asic-status-2.html#post16987
From Josh:
I wonder why they sacrificed the 1k chips for testing, if they can't even fully test them? It was only a few days ago that they entered testing phase. It would have made more sense to save the 1k chips, wait the 5 days, and be able to deliver that many more chips to customers instead of making them wait even longer. Me thinks something else may have happened, but that's pure speculation.
https://forums.butterflylabs.com/announcements/692-bfl-asic-status-2.html#post16987
From Josh:
Quote
4 March 2013 Update
Today the bumped wafers were confirmed at the packaging facility and they have been "bumped nicely," so all is well as far as bumping goes. Packaging is currently scheduled to be done on Wednesday, although that's subject to change, I don't see any reason that is going to change at the moment.
The chips achieved 350 MHz hashing on 4 engines as well. We are going to have to wait until the chips are packaged to take the chips higher than that with more cores, as the test rig is not able to supply enough power and there are some wire bond issues that make it unstable beyond that. Once the chips are packaged, they will be tested more fully. Regardless, the chips are hashing properly and all IO appears to be correct, which is the important part. I will update when further testing is complete.
Timeline for the second set of 6 wafers is currently scheduled several days out after we have a successful test of the packaging (they'll have to make their way through bumping and packaging as well) and then the remainder is scheduled for ~7 days after that. I can't be more specific with regards to a date on the 6 wafers yet, as I don't have specific dates. I will update once I do.
Today the bumped wafers were confirmed at the packaging facility and they have been "bumped nicely," so all is well as far as bumping goes. Packaging is currently scheduled to be done on Wednesday, although that's subject to change, I don't see any reason that is going to change at the moment.
The chips achieved 350 MHz hashing on 4 engines as well. We are going to have to wait until the chips are packaged to take the chips higher than that with more cores, as the test rig is not able to supply enough power and there are some wire bond issues that make it unstable beyond that. Once the chips are packaged, they will be tested more fully. Regardless, the chips are hashing properly and all IO appears to be correct, which is the important part. I will update when further testing is complete.
Timeline for the second set of 6 wafers is currently scheduled several days out after we have a successful test of the packaging (they'll have to make their way through bumping and packaging as well) and then the remainder is scheduled for ~7 days after that. I can't be more specific with regards to a date on the 6 wafers yet, as I don't have specific dates. I will update once I do.
I wonder why they sacrificed the 1k chips for testing, if they can't even fully test them? It was only a few days ago that they entered testing phase. It would have made more sense to save the 1k chips, wait the 5 days, and be able to deliver that many more chips to customers instead of making them wait even longer. Me thinks something else may have happened, but that's pure speculation.
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