Topic: BitFury 110GH/s per rack? - page 2. (Read 11047 times)

Hey, at least I get to share with zhoutong the dubious honor of having had my name verbified by the forum users.  I guess that's something!


Just guessing, but he probably daisy-chains the hashers in each clock region, runs them one step out-of-phase with each other, and has a single bram feed them k-values which get passed along from one hasher to the next, bucket-brigade style.  My very first design -- which was bit-serial (really bad idea!) -- worked that way.


The DNA register is just a shift register; it's trivial to swap it out for an SRL32 in fpga_editor.

By the way, these guys have documented the bitstream format and made tools that turn .bit files back into .ncd files -- even (completely illegible) .v files in some cases.


I don't think Xilinx wants the liability that comes with being a certificate authority -- especially one whose certificates can't be revoked because they're burned into millions of dollars worth of silicon.  You can bootstrap similar schemes yourself on Virtex-6 and above; see section 6 of this paper.


I wouldn't trust them if I were you.  It's completely trivial to extract the AES key from Xilinx devices, even Spartan-6.  Even battery-backed ram.  Only one power-on is required, and the equipment isn't expensive (if you rent it it's downright cheap).  They didn't fix this problem until Virtex-6.


Quite prescient of you -- stay tuned.  But I'm not sure how well this would work for you -- with a highly-rolled design it's easy for an attacker to tell the difference between countermeasure circuits and the actual hashers -- just look for the pattern and chop out anything irregular.  Once you've got it down to a few hundred slices it's easy to figure out where the inputs and outputs are and what they mean. Replicate that block, stitch it back together and the game's over.

On the other hand, you guys make your own hardware -- that's a big advantage when it comes to anti-piracy measures.  You might be better off looking into ways to leverage that, like a tamper-proof housing around the spartan that erases the bitstream if breached and extra circuits to thwart power-analysis attacks.  People are also less likely to try to reverse engineer your work if they have to take apart and possibly damage a box they've paid $100,000 for!

i think it's really not important to a accurate number. our cores are using 256 slices. but only 64 clocks.


by special optimization on the arithmetic and setup pre-processors (certainly, inside the FPGA), it can reduce 3-4 calculate rounds.


i think it's very close to us.

I find it amusing people are comparing a non released product to something that is already operating and outputting real world numbers.

No. Completely unrelated.

A guy or gal named Valery just responded to a personal email of mine with the clarification that they are indeed talking about 8 x 30 slices,
the same number a count on their screen shot comes up with.
In other words, 8 x 32 was a typo, which they have corrected on their website by now.

Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

42? (i have nothing useful to say... sorry.)

My point was, that 8 x 32 is not 240. It is 256.
If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240.
Or am I missing the point here?

at present no comment, but
much easier than you think... 

i believe because we did just exactly the same.  2X 64cycle SHA256 core in 8X32 area, include control logic,  timing report is much over 300MHz.
the coding work is easy(maybe less than 50 lines.) but write the UCF files used month of time, and still have some small bugs now. 

On their website, they state:
Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.

I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up. 

So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe.
Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement.

How were you solving the overheat? Liquid nitrogen?

by our review, not only heat.
some thing other limit break out when we solved over-heat.

The Cairnsmore are cheaper, but that's a time limited special offer (at least according to them). At the regular price of US$1280, they'd be more expensive.

No, Enterpoint's cairnsmore1 pre-order prices are cheaper. It will do at the very least 800 Mh/s with an average-performing bitstream (more likely 850 Mh/s) at $640. This is 1.25 Mh/s/$ (more likely 1.33 Mh/s/$). BitFury is more expensive at 1.22 Mh/s/$.

I guess one could say BitFury is cheaper on a technicality: Cairnsmore1 has not shipped yet.

Did she also have an ass like that?

The woman, my first love had a tattoo of a butterfly a bit like this, so I am attracted to anything to do with butterflies and because of this, Butterfly Labs have won my heart as soon as I heard about them.

Someone's being a little extra pissy this morning. I didn't see the sticky indicating that no FPGAs could be discussed unless it beats the BFL offerings.

I wouldn't say this is uncompetitive at all. If they built it for US$90K and it gets 110GH/s, it's the cheapest of the LX150 options. The power consumption is pretty high, but I'd be interested to see the actual breakdown. 110GH/s÷360 = 305MH/s, and they claim their 300MH/s bitstream consumes 12W which seems reasonable compared to other LX150s. For 360 FPGAs, that's 4.32kW. The remainder at 2.7kW seems a little high for the microcontroller backplanes, Atom boards and inefficiencies in the power supplies.

As for the price, it's moot since they haven't sold any at that price as far as anyone here knows. For that matter, BFL isn't selling their minirigs either. At this point they're just taking people's money as an interest free loan for an indeterminate amount of time.

Any word yet if the low end -7 series will have metal heatspreader.  I would imagine you could get 20 to 30 Mhz more out of the Spartans if it like trying to pull that heat through the low conductivity plastic package.

28nm is still very far away.

on the -7 series the routing resource is far different form spartan6, so this design can not be simply transplant to -7 series, but this architecture is still useful.

Indeed, specialise in heating/cooling systems like that, make the FPGA/ASIC's modules, well, modular, publish specs, get me on the board of directors, lol. You got yourself a killer niche here.

I actually want to buy myself a few of those rigs minus FPGA modules.