What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.
Which software is used to design the chips? Where do the models for the gates come from?
FYI: I am almost certain this is a scam.
These factors all contribute to the inexpensive cost:
1. 130nm node size. As the mainstream switches to 28nm, the 130nm existed for so long that even many smaller foundries could do it very well. The intense competition of manufacturing in China brings the price of everything down, including ICs. Though we chose the larger and more reliable foundry, their evaluation of the price of 130nm full-mask and MLM is still near the price in this main thread.
2. MLM(Multi-Level-Mask). Compared to full-mask, this technology reduces the cost of mask-set to half with the exchange of increasing the margin cost by about 40%. This is a good deal for us because the margin cost of chips themselves is one of the lowest cost in our budget.
3. Low EDA license fees and low labor cost in China.
4. We ourselves did most of the RTL design, optimization and simulation.
The RTL is written in Verilog.
Frontend: We use VCS for simulation, Verdi for debugging, DC for synthesize.
Backend: We use ICC for P&R, Calibre for DRC/LVS check, virturso for layout merge, StarRCXT for RC extraction and PrimeTime for STA.
Formality is used to verify the netlist. We also do some simulation directly on the netlist but it is very slow compared to that on the RTL phase, so many possible cases of the state machine couldn't be covered. Formality is needed to increase the confidence of the synthesize results.
By models of the gates, I guess you mean technology libraries. They are provided by our foundry indirectly from the foundry agent.
The PLL IP module is also provided by them.
Please PM me with your e-mail address and ask for more documents and information if you feel necessary. Thanks.
I have played with mentioned softwares, shown pictures looks coherent. In my opinion success probability would be high for such approach. Tool names, etc match... I will decode what that means - VCS - is simple stuff - it's rather top-level verilog simulator. Verdi - I don't get why you need a debugger.
DC is Synopsys Design Compiler - which is usually shipped as part of ICC (top-level) - Synopsys IC Compiler.
Synopsys IC Compiler basically enables you to feed in gates and get what is on picture, and that is rather quick operation, once your RTL is good. Good sides - it would do layout for you, bad part - manual layout would dramatically for sha256 outperform automated layout, but require dramatically more time + more understanding of low-level stuff, like maintaining heights inside of chip, etc.
Calibre - is Mentor Graphics Calibre - de-facto standard for Design Rules Check (DRC) and Layout Versus Schematics (LVS) checks - DRC is basically checking of multiple design rules mentioned by fab, and LVS is verifying layout vs its schematic equivalence. Usually if you wrote (or get from fab) correct technology file for Calibre that means that your design IS MANUFACTURABLE.
Virtuoso - is a full-featured suite from Cadence - for IC design, compilation, etc... So all could be done in Virtuoso, but package at my taste looks like pain in ass...
Synopsys StarRXCT for RC extraction - RC extraction - is one of important things for design verification, as it provides exact delays caused by capacitors and resistances existing in circuit. Basically it eats layout images, and generates files for further simulations (say for example SPICE circuit can be extracted with parasitic values).
Synopsys Primetime is powerful tool to get perform timing analysis taking data from StarRXCT.
Also there can be run SPICE simulation after StarRXCT to get power consumption for the design.
I am no way affiliated with friedcat, so I can basically confirm for public plausibility of mentioned data, if they (friedcat) will decide to publish PrimeTime reports for
their design and spice simulation to get power consumption...
ALSO PLEASE NOT - THAT LAST THING IS _MANDATORY_ FOR THEM - PERFORM POWER ANALYSIS...... IT IS LIKELY THAT YOUR DESIGN WOULD NOT WORK ON MENTIONED CLOCKS
IN PRIMETIME JUST BECAUSE NOT ENOUGH POWER BYPASS WAS PLACED, AS IN THIS PART DESIGN BECOMES MUCH MORE DIFFICULT THAN PLACING SAY CPU, WHERE TOGGLE RATES DEFINITELY MUCH LOWER. IF YOU IGNORE THIS - IT MAY HAPPEN THAT YOU GET 1/2 or 1/3 OF CLOCK IN REAL DESIGN. Power Integrity could be done with Spice or maybe better specialized tools (easier)... Maybe quick simulation of single round would help you in Synopsys HSPICE or full-design simulation in Mentor MachTa (but this I don't know for sure, how well MachTa suites for power consumption analysis - I think better is work on smaller but regular portion of design using HSPICE, as full-chip sim will go for ages I believe).
MLM asic chip basically tells me that TSMC is foundry, as they widely advertised MLM technology, where you can reduce masks costs 2 times or 4 times or possible even more (it was not advertised though), when you can put several layers of chips on same reticle.