[CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support - page 14.

vs3

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Quote from: ernie- on February 04, 2014, 07:24:14 PM

Quote from: vs3 on February 03, 2014, 07:03:36 PM

Quote from: ernie- on February 03, 2014, 06:31:34 PM

Quote from: vs3 on February 03, 2014, 05:52:14 PM

I've got some goodies too! :-)

Thanks Zefir!

Are you going to to an open source board design for it?

I am considering that. But no promises yet.

I have a little bitter taste left from the previous open-source design - which took a lot of work and energy to get it to its current and complete state, and I see a lot of people enjoying the benefits of it, except that I'm still paying the bills. And I still owe to the other people (including Luke) who did such an awesome work to get it to where it currently is.

Sorry, I am not up on that story, what happened to the project, how come it cost you money?

Well, despite our best wishes it turns out that nothing is free in life (well, maybe with the exception of the cheese in the trap). Components aren't free. Boards aren't either. Each sample boards run alone was $400-800 when you add all components and stencils and shipping (yeah, overnight wasn't cheap). Just as a reference - the first usable board was the 7th tested and checked in design. And that's just a portion of the inevitable part that had to be paid with money right away - I'm not even mentioning here the insane amount of work that had to be done in that short time.
So - yeah, it did cost a lot of money, or as a friend of mine put it - I could've gotten a new car for that much money.

Anyways, that's a side story and doesn't belong in this thread. If you want PM me and we can continue there. But in essence - do a search for "nanofury" on the forums and you'll see how many people have used the design, and then look the bitcoin address and see how much donations it received since November.

ernie-

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Activity: 252

Merit: 250

Quote from: vs3 on February 03, 2014, 07:03:36 PM

Quote from: ernie- on February 03, 2014, 06:31:34 PM

Quote from: vs3 on February 03, 2014, 05:52:14 PM

I've got some goodies too! :-)

Thanks Zefir!

Are you going to to an open source board design for it?

I am considering that. But no promises yet.

I have a little bitter taste left from the previous open-source design - which took a lot of work and energy to get it to its current and complete state, and I see a lot of people enjoying the benefits of it, except that I'm still paying the bills. And I still owe to the other people (including Luke) who did such an awesome work to get it to where it currently is.

Sorry, I am not up on that story, what happened to the project, how come it cost you money?

papamoi

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Activity: 378

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there is this project

we ll try to adapt it for coincraft a1 if possible

https://bitcointalksearch.org/topic/m.4593806

Dexter770221

legendary

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And here is my beauty:
http://imgur.com/M72XLOq
Some borring uC wiring left but is almost done Wink

Bicknellski

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Activity: 924

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Quote from: vs3 on February 03, 2014, 07:03:36 PM

Quote from: ernie- on February 03, 2014, 06:31:34 PM

Quote from: vs3 on February 03, 2014, 05:52:14 PM

I've got some goodies too! :-)

Thanks Zefir!

Are you going to to an open source board design for it?

I am considering that. But no promises yet.

I have a little bitter taste left from the previous open-source design - which took a lot of work and energy to get it to its current and complete state, and I see a lot of people enjoying the benefits of it, except that I'm still paying the bills. And I still owe to the other people (including Luke) who did such an awesome work to get it to where it currently is.

vs3. You are always welcome to throw some of your sweat into our project we'd love to have you. Grin

vs3

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Activity: 622

Merit: 500

Quote from: ernie- on February 03, 2014, 06:31:34 PM

Quote from: vs3 on February 03, 2014, 05:52:14 PM

I've got some goodies too! :-)

Thanks Zefir!

Are you going to to an open source board design for it?

I am considering that. But no promises yet.

I have a little bitter taste left from the previous open-source design - which took a lot of work and energy to get it to its current and complete state, and I see a lot of people enjoying the benefits of it, except that I'm still paying the bills. And I still owe to the other people (including Luke) who did such an awesome work to get it to where it currently is.

ernie-

sr. member

Activity: 252

Merit: 250

Quote from: vs3 on February 03, 2014, 05:52:14 PM

I've got some goodies too! :-)

Thanks Zefir!

Are you going to to an open source board design for it?

vs3

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Activity: 622

Merit: 500

I've got some goodies too! :-)

Thanks Zefir!

intron

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Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Received 50 A1 samples, thank you for that Zefir.

totalslacker

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Quote from: zefir on February 02, 2014, 03:59:30 AM

Quote from: totalslacker on February 01, 2014, 04:20:07 PM

So I'm in the final stages of PCB layout here (hoping to release the board today or tomorrow). Still one question is pending however: are there any sequencing restrictions on bringing up the IO/analog and core voltage supplies for the A1? I'm currently planning to bring up IO, then the core supply - will this be ok?

I've asked Bitmine as well and the question has been forwarded to engineers but no reply as yet.

There are no related restrictions documented or known and I am not aware that anyone from the working designs is keeping some defined bring-up order. The only requirement documented is the reset sequence (1s low, then 1s high before first command is sent).

OK, thank you!

Cheshyr

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Quote from: zefir on February 02, 2014, 03:59:30 AM

So far it seems I have been the only one using it - if and when the user base broadens, the correct way is to a) clean the code up, b) rebase it on current cgminer head, and c) get it accepted upstream. Since this needs some initial and ongoing maintenance effort, I need to know if anyone is using the driver as-is for own designs.

My driver is meant to attach to a system's SPI port directly and most probably will serve only as template for full featured drivers or initial testing.

I've seen mention of 2 different single-chip or direct-connect boards in this thread so far, and 2 of our projects involving the A1 are also going to start as USB-SPI direct. My only sadness is that the bitmine.ch branch doesn't have MCP2210 support or official RPi support, and the main cgminer does, so I've got features in both versions that I want to use. I started diffing them last night, but wanted to check the procedure first. Thanks.

loshia

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Quote from: ?? on ??

Quote from: loshia on February 02, 2014, 06:58:32 AM

I am wandering how you do that having in mind what the usual reject rate is at btcguild?

Marto had his A1 boards ready since 18th December, that's how he's so quick, then he fine tunes them by adding capacitors to the pre-production models. Martin told me once they may look ugly but they work better that way! Later production runs replace the ugly big capacitors with micro ones. What he finally delivers don't look like the ugly pre-production pictures on the web site! Everything looks professional like it came from a big manufacturer. Wink

It is software dude. Both pic and cgminer. Hw errors may be capacitors related Wink

loshia

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Quote from: marto74 on February 02, 2014, 04:04:51 AM

12 hour stable

photo share

Insane reject ratio of 0.14% only Shocked

I am wandering how you do that having in mind what the usual reject rate is at btcguild?
And hw error % looks perfect also.

marto74

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12 hour stable

photo share

zefir

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Quote from: loshia on February 02, 2014, 02:39:34 AM

Quote from: Cheshyr on February 02, 2014, 12:54:55 AM

So how is everyone handling the cgminer integration?

The https://github.com/bitmine-ch/cgminer branch that Zefir put so much excellent work into is a bit deviant from the https://github.com/ckolivas/cgminer I'd been using. There are features in the ckolivas version that I'd like to use, so what's the standard procedure here? Fork/branch ckolivas version, integrate the A1 bits, then see what it takes to pull and merge it back?

Depends on the design and i/o USB communication protocol. There will be patch fro Technobit I beleive but it will be specific to their design. Actually there is some code released in their latest version

So far it seems I have been the only one using it - if and when the user base broadens, the correct way is to a) clean the code up, b) rebase it on current cgminer head, and c) get it accepted upstream. Since this needs some initial and ongoing maintenance effort, I need to know if anyone is using the driver as-is for own designs.

And that is one point: all designs currently being worked on are based on existing drivers already integrated in cgminer. Take marto74's for example: the uC on the 8-chip board will encapsulate the control of the A1 chips and to cgminer that board will look like any other HEX based one, fully accessible with the existing driver. Same goes for WASP, burnin, intron. My driver is meant to attach to a system's SPI port directly and most probably will serve only as template for full featured drivers or initial testing.

Quote from: totalslacker on February 01, 2014, 04:20:07 PM

So I'm in the final stages of PCB layout here (hoping to release the board today or tomorrow). Still one question is pending however: are there any sequencing restrictions on bringing up the IO/analog and core voltage supplies for the A1? I'm currently planning to bring up IO, then the core supply - will this be ok?

I've asked Bitmine as well and the question has been forwarded to engineers but no reply as yet.

There are no related restrictions documented or known and I am not aware that anyone from the working designs is keeping some defined bring-up order. The only requirement documented is the reset sequence (1s low, then 1s high before first command is sent).

loshia

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Activity: 1610

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Quote from: Cheshyr on February 02, 2014, 12:54:55 AM

So how is everyone handling the cgminer integration?

The https://github.com/bitmine-ch/cgminer branch that Zefir put so much excellent work into is a bit deviant from the https://github.com/ckolivas/cgminer I'd been using. There are features in the ckolivas version that I'd like to use, so what's the standard procedure here? Fork/branch ckolivas version, integrate the A1 bits, then see what it takes to pull and merge it back?

Depends on the design and i/o USB communication protocol. There will be patch fro Technobit I beleive but it will be specific to their design. Actually there is some code released in their latest version

Cheshyr

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Activity: 168

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So how is everyone handling the cgminer integration?

The https://github.com/bitmine-ch/cgminer branch that Zefir put so much excellent work into is a bit deviant from the https://github.com/ckolivas/cgminer I'd been using. There are features in the ckolivas version that I'd like to use, so what's the standard procedure here? Fork/branch ckolivas version, integrate the A1 bits, then see what it takes to pull and merge it back?

totalslacker

newbie

Activity: 26

Merit: 0

So I'm in the final stages of PCB layout here (hoping to release the board today or tomorrow). Still one question is pending however: are there any sequencing restrictions on bringing up the IO/analog and core voltage supplies for the A1? I'm currently planning to bring up IO, then the core supply - will this be ok?

I've asked Bitmine as well and the question has been forwarded to engineers but no reply as yet.

Thanks for any help!

MrTeal

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Nice Marto. What's the power draw like at 30GH/s per chip, and what voltage are you running?

marto74

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screen capture software

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