Hm. They own Nallatech too. I was unaware of that. I always thought they were just the power connector guys.
Topic: DIY FPGA Mining rig for any algorithm with fast ROI - page 68. (Read 99458 times)
Wonder what this means for bittwares fpga mining offerings....
https://www.molex.com/molex/news/new_display_news.jsp?channel=New&channelId=-8&oid=2376&pageTitle=Molex+Announces+Acquisition+of+BittWare
Code:
Molex Announces Acquisition of BittWare
That is certainly interesting. In my experience such acquisitions usually kill little projects like this, but I would be happy to be surprised.
Wonder what this means for bittwares fpga mining offerings....
https://www.molex.com/molex/news/new_display_news.jsp?channel=New&channelId=-8&oid=2376&pageTitle=Molex+Announces+Acquisition+of+BittWare
Code:
Molex Announces Acquisition of BittWare
@tromp - now that I found it I see it is quite old, so perhaps it was already implemented in the latest solvers http://www.cs.cmu.edu/~dga/crypto/cuckoo/analysis.pdf
That was already implemented back in early 2014, even before the Cuckoo Cycle paper appeared in BITCOIN2015.
Talk about old!
Yes, the barrier to entry is far greater than any other popular form of mining and, currently, there is no community. That said a couple of members here are starting to have slightly open discussions that it seems even they are realizing benefits themselves in participating.
Like fpga's the work on fpga mining is incredibly parallelized with each person interested having to solve the very same problems everyone else is solving or has already solved. Understandably greed is a stronger motive than the altruism that started the open source projects that this technology stands on the shoulders of.
Ironically, for fpga's that parallelization is what makes them so efficient. The same cannot be said of the lack of community within fpga software development.
Like fpga's the work on fpga mining is incredibly parallelized with each person interested having to solve the very same problems everyone else is solving or has already solved. Understandably greed is a stronger motive than the altruism that started the open source projects that this technology stands on the shoulders of.
Ironically, for fpga's that parallelization is what makes them so efficient. The same cannot be said of the lack of community within fpga software development.
I just created a telegram group about FPGA Mining: https://t.me/joinchat/GG5lnkwkEaKOIzwXrFkodw
It would be cool to find like-minded people.
Hey,
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
Just curious. Say he gets a tutorial and learns some fpga programming. Dont you need knowledge of how hashing actualy works as well to implement it?
Yes, the barrier to entry is far greater than any other popular form of mining and, currently, there is no community. That said a couple of members here are starting to have slightly open discussions that it seems even they are realizing benefits themselves in participating.
Like fpga's the work on fpga mining is incredibly parallelized with each person interested having to solve the very same problems everyone else is solving or has already solved. Understandably greed is a stronger motive than the altruism that started the open source projects that this technology stands on the shoulders of.
Ironically, for fpga's that parallelization is what makes them so efficient. The same cannot be said of the lack of community within fpga software development.
I'm sorry, due to other commitments I'm unable to finish the reply below. Sorry for the incompleteness. I may be able to follow up in the coming weeks.
The investment in technology mail fail not only because it was a scam or something not physically realizable. It may well be doable relatively easy, but fail because the management developed substance abuse problem or the people with real required knowledge either departed or were never on the team.
There are many things that one can surmise from simple observation of progressing dyslexia or repetitive mistakes.
Secondly, it really cuts both ways. Some users here may have supremely effective ways of debt collection, e.g. charging one finger per week for overdue delivery.
I think you precisely missed my statement about being pedantic. I knew what you meant and was saying that everyone reading the marketing speak knew what they meant. They used the wrong unit but everyone still understood, and nothing of value was lost other than it clearly irritates you.
Certainly, not "everyone reading". I'm not as pessimistic as nsummy to say 95%, but somewhere between 25% and 50% of readers will get confused. Whether that's intentional or accidental is a different story.The investment in technology mail fail not only because it was a scam or something not physically realizable. It may well be doable relatively easy, but fail because the management developed substance abuse problem or the people with real required knowledge either departed or were never on the team.
There are many things that one can surmise from simple observation of progressing dyslexia or repetitive mistakes.
Agree that everyone here that doesn’t do this type of work themselves should proceed cautiously and be responsible for their own destiny. I’m amazed when I see people immediately pop up and want to order 100 of something with zero understanding or evidence. Fear of missing out or hoping to be the first in and get rich before the jig is up?
Firstly, some users here have way more play money than the others.Secondly, it really cuts both ways. Some users here may have supremely effective ways of debt collection, e.g. charging one finger per week for overdue delivery.
..
I figured out how he got 17Gh/s. It's 34 cores 35K luts each with reduced bus width (not the full 1600) operating at 500mhz. He only placed registers at the start of the round, not in the round. That plus some floorplanning to keep the fmax high.. I could probably hit the same number now that I see it
You’re supposed to keep the cats in the bag! Floorplanning seems to be totally overlooked by a lot of the published crypto work I’ve seen on big FPGAs, which is very unfortunate for performance. Place and route is not magic, giving it guidance is quite helpful.
@tromp - now that I found it I see it is quite old, so perhaps it was already implemented in the latest solvers http://www.cs.cmu.edu/~dga/crypto/cuckoo/analysis.pdf
..
I figured out how he got 17Gh/s. It's 34 cores 35K luts each with reduced bus width (not the full 1600) operating at 500mhz. He only placed registers at the start of the round, not in the round. That plus some floorplanning to keep the fmax high.. I could probably hit the same number now that I see it
It's kind of moot with asics for equihash and ethash. Unless there's some other large mem algo I'm not aware of.
There is.
https://github.com/tromp/cuckoo
Not aiming to be argumentative because I never studied it deeply, but wasn’t there a strong analysis done that showed a large GPU optimization (and by extension FPGA/asic) for your cuckoo algorithm existed? I never saw a response from you on that.
The Cuckoo Cycle webpage lists several performance claims. Which of the claims does the strong analysis refute? And why haven't you claimed the corresponding large bounty?
It wasn’t my analysis. I’ll try to dig it back up, I have no personal involvement or basis for believing it, other than it comes up every time someone asks about using Cuckoo as an ASIC resistant algorithm for a crypto. I’ve assumed it convinced others and that’s why I continue to be unaware of any large coins using cuckoo. It could also be general distrust of newer (relatively speaking) algorithms that haven’t been thoroughly studied. Regardless I’d love to get the explaination of the flaw in the argument.
It's kind of moot with asics for equihash and ethash. Unless there's some other large mem algo I'm not aware of.
There is.
https://github.com/tromp/cuckoo
Not aiming to be argumentative because I never studied it deeply, but wasn’t there a strong analysis done that showed a large GPU optimization (and by extension FPGA/asic) for your cuckoo algorithm existed? I never saw a response from you on that.
The Cuckoo Cycle webpage lists several performance claims. Which of the claims does the strong analysis refute? And why haven't you claimed the corresponding large bounty?
Hey,
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
Just curious. Say he gets a tutorial and learns some fpga programming. Dont you need knowledge of how hashing actualy works as well to implement it?
My god. I want to take part in this....
But there has to be cheaper alternatives? :/
But there has to be cheaper alternatives? :/
it seems there gan, I've read in the thread next to there is a cheap and simple way of mining it through hanpone, but not know when it will be launched.
thank you
Hey,
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
Im looking for a all-in-one tutorial buy site + explanation how work FPGA
It is better to buy the version at 5k or 1k?
What tests were you able to do and how do you make it work?
Really thanks !!
It's kind of moot with asics for equihash and ethash. Unless there's some other large mem algo I'm not aware of.
There is.
https://github.com/tromp/cuckoo
Not aiming to be argumentative because I never studied it deeply, but wasn’t there a strong analysis done that showed a large GPU optimization (and by extension FPGA/asic) for your cuckoo algorithm existed? I never saw a response from you on that.
Btw, did some reading on algebraic logic minimization last night along with a couple other techniques. This is already done, automatically, during synth (but can be turned off). Seeing the process, yes, it's something that could be added to simplify logic circuits. HOWEVER, Vivado already does it! Starting to question OP and if this bittware account is even really bittware. I might have to put my foot in my mouth in 18 days, but the more I look at it, the more I'm thinking it's not possible. Elaborate scam?
Using Logic Friday is also a valid approach, but I don't understand how that gets translated back into Vivado. Unless the coding is done at gate level, I don't know how it would be done. Logic Friday is also limited to 16 input and 16 output truth tables. The Espresso algorithm is also the correct logic reduction scheme. Logic Friday uses that algorithm for logic reduction. There is also C code for the algorithm that would not have truth table size restrictions.
Xilinx does not give their algorithm methods to the public. Maybe Synopsys would have some features I am not familiar with.
What does the OP gain by making this up? Only way I can think that they would profit is if they are getting a profit share of the hardware sales.
There are a couple of espresso minimizers i've found that would do 256 in / 256 out. One allowed VHDL output. Might be possible to just take an entire design that you like and starting at the one side go through and simplify the logic 256 ins / 256 outs at a time. (See you next tuesday) Learning how to do it by hand, it was very easy to see that a computer could iterate over the logic and reduce it much faster and to a more minimal level. There's a few pieces of K-Map software too.
I'm not sure he would need to do an entire design (as in the whole chip), only a single core, then iterate that core over multiple defined regions.
Synopsis has synplify, but it's not clear if it would be better or worse than vivado. I would think vivado would be able to better convert code into bits ideal for a 9P.
Btw, did some reading on algebraic logic minimization last night along with a couple other techniques. This is already done, automatically, during synth (but can be turned off). Seeing the process, yes, it's something that could be added to simplify logic circuits. HOWEVER, Vivado already does it! Starting to question OP and if this bittware account is even really bittware. I might have to put my foot in my mouth in 18 days, but the more I look at it, the more I'm thinking it's not possible. Elaborate scam?
Using Logic Friday is also a valid approach, but I don't understand how that gets translated back into Vivado. Unless the coding is done at gate level, I don't know how it would be done. Logic Friday is also limited to 16 input and 16 output truth tables. The Espresso algorithm is also the correct logic reduction scheme. Logic Friday uses that algorithm for logic reduction. There is also C code for the algorithm that would not have truth table size restrictions.
Xilinx does not give their algorithm methods to the public. Maybe Synopsys would have some features I am not familiar with.
What does the OP gain by making this up? Only way I can think that they would profit is if they are getting a profit share of the hardware sales.
To the guy who said he was thinking of doing a FPGA farm and flew around the world to meet with investors. I'm located in the US.
I'm here and listening, PM me and we can make something work. I can build out an actual mining farm
I'm here and listening, PM me and we can make something work. I can build out an actual mining farm
What speed could be achieved with x13 do you think?
It's kind of moot with asics for equihash and ethash. Unless there's some other large mem algo I'm not aware of.
There is.
https://github.com/tromp/cuckoo
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