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Topic: First GENUE LTC FPGA - page 2. (Read 3361 times)

hero member
Activity: 742
Merit: 500
Its as easy as 0, 1, 1, 2, 3
September 20, 2013, 01:47:10 AM
#30
Boy howdy...this could be a game changer if legit
unless it is a asic device, it wont be a game changer

for those who know nothing about chip design, First FPGA, then to hard silicon. FPGA allows you to work the bugs out of your design before you dump 25K to have it masked in silicon.
2nd off, Scrypt is completely possible to build an ASIC for. math is what computers do best. Scrypt just requires some external ram. big deal. ram is cheap. I dont doubt the authenticity of this. there are a couple other people working on fpga scrypt machines. They just arent posting their work here for kudos and warm pats on the back.


*pats the project dev on the back* bravo, the numbers do look to be in the realm of possibility.
full member
Activity: 238
Merit: 100
Inject Its Venom Into Your Veins
September 20, 2013, 01:42:40 AM
#29
O.M.G :-O     Super Jelllyyyy!!!! Keep us updated!!!
full member
Activity: 205
Merit: 100
Cheif Oompa Loompa.
September 20, 2013, 01:40:15 AM
#28
Boy howdy...this could be a game changer if legit
unless it is a asic device, it wont be a game changer

for those who know nothing about chip design, First FPGA, then to hard silicon. FPGA allows you to work the bugs out of your design before you dump 25K to have it masked in silicon.
2nd off, Scrypt is completely possible to build an ASIC for. math is what computers do best. Scrypt just requires some external ram. big deal. ram is cheap. I dont doubt the authenticity of this. there are a couple other people working on fpga scrypt machines. They just arent posting their work here for kudos and warm pats on the back.
hero member
Activity: 798
Merit: 1000
‘Try to be nice’
September 20, 2013, 12:59:58 AM
#27
Quote from: beekeeper link=topic=297533.msg3193041#msg3193041 date=13796Scrypt4
Hi,
I just got my old thread locked, showing a fpga hashing at 22 Khs, lol. Bord can do really more..
 https://vimeo.com/m/74955720

I'm considering going on reddit with full story!

Twas not me, meaning John K most likely locked your original thread. *Wonders...*

Ha ha does not wonder , these guys get a little sensitive about fpga and ASIC when they look like getting out to the real market .

KnC will be working on a sCrypt asic just as soon as this party is over .  I expect .
newbie
Activity: 16
Merit: 0
September 20, 2013, 12:48:37 AM
#26
22 kh/s with 1,5$ for single kh/s makes 33$. Sorry, I don't buy that unless you get FPGAs from factory's back door. ~20$ costs 8 layer PCB in China, that you need to properly route all DDR3 signals from FPGA. Plus a device cost, plus assembly.
sr. member
Activity: 432
Merit: 250
September 19, 2013, 11:46:08 PM
#25
Boy howdy...this could be a game changer if legit
unless it is a asic device, it wont be a game changer
legendary
Activity: 1610
Merit: 1000
Well hello there!
September 19, 2013, 11:45:28 PM
#24
Boy howdy...this could be a game changer if legit
hero member
Activity: 686
Merit: 504
always the student, never the master.
September 19, 2013, 10:19:08 PM
#23
it look very ugly, when complete can you give better look?

my sources indicate this video was of the first model, and the current prototype has 8  chips per board. their goal is 1.2  m/hs per board @ 150 watts fyi. this is definitely one to watch.
sr. member
Activity: 432
Merit: 250
September 19, 2013, 10:08:44 PM
#22
it look very ugly, when complete can you give better look?
sr. member
Activity: 406
Merit: 250
September 19, 2013, 08:47:24 PM
#21
Well I'll be damned.

Weird stuff.

A google search query of the device ID's ("idVendor=0x1234" "idProduct=0x1010") yields many links to z.download.csdn.net where such information is referenced almost exactly, some kind of chinese internet forum. Apparently this has something to do with "STM32", which is a model of ARM Cortex MCUs. It seems to me the device id's referenced might be the ones of those devices.

Or maybe it's a generic idVendor and idProduct, but those were the only matches I could find.

Otherwise I could not find any correlation between what he posted and anything currently findable by google.

I have to say, it's a mystery. Maybe he does have an fpga miner, but it's single-threaded and does not resolve any of the scrypt fpga-mining issues that makes it so unprofitable so is more or less exactly worthless.
legendary
Activity: 2590
Merit: 2156
Welcome to the SaltySpitoon, how Tough are ya?
September 19, 2013, 08:09:34 PM
#20
Hi,
I just got my old thread locked, showing a fpga hashing at 22 Khs, lol. Bord can do really more..
 https://vimeo.com/m/74955720

I'm considering going on reddit with full story!

Twas not me, meaning John K most likely locked your original thread. *Wonders...*
hero member
Activity: 686
Merit: 504
always the student, never the master.
September 19, 2013, 08:05:16 PM
#19
Nah r3wt that's not how I am. Tongue

Nice that at least we've come to an agreement.

Indeed, let's see what he says.

Ha, right on bro. agreed. and btw, for the record i'm a currently in "scammer rehab". you probably can't trust me as far as you can throw me, but at the very least people can talk to me in a civilized manner i would think. I'm not a bad person i just took advantage of some people and i thought it was high time i admitted what most other people knew. now i got the scam tag and all my coins and projects are going to die. i challenge all these other "dev's" to admit their scams and how much they make on these premine pump and dumps. every coin dev on the forum would have a scam tag
sr. member
Activity: 406
Merit: 250
LTC
September 19, 2013, 08:01:10 PM
#18

Post the source to test_miner.py, since all it is is a mining client and would not release any confidential information. If it shows legitimate USB or serial port interfacing code of some sort then I'll believe you.

Why not.
But this is last time I will answer such a direct question. The rest is classified. The code is really crappy since it is part of some iteration which was tested long ago:

Quote
import usb.core
import usb.util
import time
from threading import Thread, Event, RLock
import sys
import re
import struct

# find our device
dev = usb.core.find(idVendor=0x1234, idProduct=0x1010)

# was it found?
if dev is None:
    raise ValueError('Device not found')

# set the active configuration. With no arguments, the first
# configuration will be the active one
dev.set_configuration()

run_app = 1

def get_time_str():
   lt = time.localtime(time.time())
   return "%d:%d:%d" %(lt.tm_hour, lt.tm_min, lt.tm_sec)

#######################################################################################      
#######################################################################################      
class   EP2_listener(Thread):
   def   __init__(self):
      Thread.__init__(self)
      self.count = [0, 0]
      self.starttime = time.time()
      self.daemon = True
   def run(self):
      global run_app
      print "[%s]EP2_listener started" % get_time_str()
      while run_app:
         ret = ''
         try:
            ret = dev.read(0x82, 64, 0, 100)
            log_msg = ''.join([chr(x) for x in ret])
            sys.stdout.write(log_msg)
         except Exception as e:
            pass      
         if len(ret) == 0:
            time.sleep(0.01)

############ startez thread #########
listener = EP2_listener()            
listener.start()
#####################################

def wr_dev_ok_err(msg):

   try:
      dev.write(1, msg, 0, 3100)
      tick = time.time()   
      while time.time() < tick + 1.0:
         try:
            ret = dev.read(0x81, 64, 0, 3100)
            retbuf = ''.join([chr(x) for x in ret])
            if re.search("OK", retbuf):
               print retbuf
               return 1
            if re.search("ERR", retbuf):
               print retbuf
               return -1
            if re.search("BUSY", retbuf):
               print retbuf
               return -2
            print "retbuf="+retbuf
         except Exception as e:
            print e
            pass
   except Exception as e:
      print e
      pass
   return 0


def get_ok():
   tick = time.time()   
   while time.time() < tick + 1.0:
      try:
         ret = dev.read(0x81, 256, 0, 3100)
         retbuf = ''.join([chr(x) for x in ret])
         if re.search("OK", retbuf):
            print "got OK:" + retbuf
            return 1
         if re.search("ERR", retbuf):
            print retbuf
            return -1
         if re.search("BUSY", retbuf):
            print retbuf
            return -2
         print "retbuf="+retbuf
      except Exception as e:
         print e
         pass
   

def wr_dev(msg):

   try:
      dev.write(1, msg, 0, 3100)
      tick = time.time()   
      while time.time() < tick + 1.0:
         try:
            ret = dev.read(0x81, 64, 0, 3100)
            retbuf = ''.join([chr(x) for x in ret])
            if len(retbuf):
               #print "retbuf="+retbuf
               return retbuf
         except Exception as e:
            #print e
            pass
   except Exception as e:
      #print e
      pass
   return 0   

def ask_op(op):
   wr_dev("Z7X,00000000%02x"% (op &0xff))
   retcode = wr_dev("Z7X,0100000200")
   return retcode
   
def memvar_dump(ram_off, len, name):

   wr_dev("Z7X,%08lx05" % ram_off)
   
   ar = []
   for j in xrange(len):
      retcode = ask_op(0x07)
      val = 0
      try:
         val = int(retcode, 16)
      except:
         pass
      ar.append(val)
   return ar   
tick = time.time()
run_once = 1
time.sleep(0.5)
print "GET_ID=%s" % ask_op(1)


########################################################
#### dll result ####
########################################################
#######################################################################################      
#######################################################################################      

def uint32(x):
   return x & 0xffffffffL

def bytereverse(x):
   return uint32(( ((x) << 24) | (((x) << Cool & 0x00ff0000) |
         (((x) >> Cool & 0x0000ff00) | ((x) >> 24) ))

def bufreverse(in_buf):
   out_words = []
   for i in range(0, len(in_buf), 4):
      word = struct.unpack('@I', in_buf[i:i+4])[0]
      out_words.append(struct.pack('@I', bytereverse(word)))
   return ''.join(out_words)

#######################################################################################      
host = "127.0.0.1"
http_port = 8337
#host = "mine.pool-x.eu"
#http_port = 8337
#host = "pool1.us.multipool.us"
#http_port = 17777
host = "mining.eu.hypernova.pw"
http_port = 9332
host = "pooledbits.com"
http_port = 8332
user = "xxxx"
password = "x"
#######################################################################################      



import json
import base64

from ctypes import cdll, byref
lib = cdll.LoadLibrary('./scrypt.dll')
#print lib
import ctypes
class Scrypt(object):
   def __init__(self):
      #self.obj = lib.say_hello()
      none = 0
   def scanhash(self, pdata, ptarget, max_nonce, c_long_last_nonce, n):
      return lib.scanhash_scrypt(pdata, ptarget, max_nonce, c_long_last_nonce, n)


scr = Scrypt()
long_polling_path = ''

import time

while 1:
   #try:
   if 1:
      #print "getwork->con_init()"
      import httplib
      conn = httplib.HTTPConnection(host, http_port, True, 10)
      #print "getwork->con_established"
      
      req = json.dumps({"method": "getwork", "params": [], "id": 'json'})
      auth = "Basic " + base64.b64encode(user+ ":" + password)
      headers = {"User-Agent": "lt_miner", "Content-type": "application/json", "Content-Length": len(req), "Authorization": auth}
      #print "getwork->req_sent"
      conn.request("POST", '/', req, headers)
      #print "getwork->req_answered"
      http_response = conn.getresponse()
      buf = http_response.read()
      #print "http_response=%s" % buf
      response = json.loads(buf)
      #print "getwork->got_data"
      if response["error"] != None:
         print "error [%s]" % response["error"]
         sys.exit(1)
      if response["result"]:
            #print("getwork() ok\n")
            work = response['result']   
            #print work
            if long_polling_path == '':
               headers = http_response.getheaders()                                 
               for (key,val) in headers:
                  if key == "x-long-polling":
                     long_polling_path = val
            if long_polling_path != '':
               do_long_poll = True
               
            ######################################################
            stime = time.time()
            last_nonce = ctypes.c_long(0)
            #n = 0
            #data = work['data'].decode('hex')
            data_orig = work['data']
            data_pt_c = work['data'].decode('hex')
            #target = work['target'].decode('hex')
            target_pt_c = work['target'].decode('hex')
            target = work['target']
            #print "data_orig=%s" % data_orig
            #print "target(full, bytereversed)=%s" % target
            print "data=%s." % data_orig[:73]
            # sys.exit(1)
            #res = scr.scanhash(data, target, 0xffff, byref(last_nonce), n )
            
            
            ######################################################
            target_short = 0xffffffff
            if len(target) > 8:
               #target_short = bufreverse(target[56:].decode('hex'))
               target_short = bytereverse(int(target[56:], 16)) ^ 0xffffffff
            target_short = 0xffff0000   #wired diff 1
            #print "target(bit_complemented)=%08lx" % target_short
            data = data_orig.decode('hex')
            data = bufreverse(data)
            #print data.encode('hex')
            
            ram_off = 4262
            wr_dev("Z7X,%08lx05" % ram_off)
            for i in xrange(19):
               word = struct.unpack('@I', data[i*4:i*4+4])[0]
               wr_dev("Z7X,%08lx06" % word)
            wr_dev("Z7X,0000000006")   #### nonce
            wr_dev("Z7X,0000ffff06")   #### range
            wr_dev("Z7X,%08lx06" % target_short)
            wr_dev("Z7X,000000000e")   
            start = time.time()
            tick = time.time() + 1.0
            while 1:
               time.sleep(0.1)
               retcode = wr_dev("Z7X,0000000000")
               if re.search("515151", retcode):
                  time.sleep(0.01)
               else:
                  retcode = wr_dev("Z7X,0000000000")
                  if not re.search("515151", retcode):
                     time.sleep(0.01)
                     delta_time = (time.time() - start) * 1000
                     print "Scanhash took %d ms" % (delta_time),
                     rram = memvar_dump(4281, 1, "nonce")
                     print "/ Approximate speed = %.2f kHash" %((float(rram[0])) / (delta_time))
                     break
               if time.time() > tick:
                  tick = time.time() + 1.0
                  print ".",

            rram = memvar_dump(4281, 1, "nonce")
            nonce = rram[0]
            res = 0
            if nonce < 0x10000:
               res = 1
            ###########################################################################
            nonce_str = "%08lx" %(nonce & 0xffffffff)
            data_new = data_orig[:156] + nonce_str[4:] + data_orig[160:]
            n = nonce - 1   
            res2 = scr.scanhash(data_pt_c, target_pt_c, nonce + 1, byref(last_nonce), n )
            if res != 0 and res2 != 0:
               f = open("succ.txt", "a")
               f.write("----NEW BLOCK----\n")
               f.write("data_orig:\n%s\n" % data_orig)
               f.write("data_new:\n%s\n" % data_new)
               f.write("nonce=%08lx\n" % nonce)
               try:
                  sconn = httplib.HTTPConnection(host, http_port, True, 10)
                  req = json.dumps({"method": "getwork", "params": [data_new], "id": 0})
                  auth = "Basic " + base64.b64encode(user+ ":" + password)
                  headers = {"User-Agent": "lt_miner", "Content-type": "application/json", "Content-Length": len(req), "Authorization": auth}
                  sconn.request("POST", '/', req, headers)
                  response = json.loads(sconn.getresponse().read())
                  if response["error"] != None:
                     print ("Server reported error: %s\n" % response["error"])
                     f.write("Server reported error: %s\n" % response["error"]);
                     time.sleep(1.0)
                  if response["result"]:
                     print "%04x accepted"  % (nonce)
                     f.write("accepted nonce=%04x %s\n"  % (nonce, response["result"]));
                  else:
                     f.write("rejected share [%s]\n" % response["result"]);
                     
               except Exception as e:
                  print("Error while uploading share e=%s\n" % e)
                  f.write("Error while uploading share e=%s\n" % e);
                  time.sleep(1.0)            
               f.write("----END BLOCK----\n\n")
               f.close()

   # except Exception as e:
      # print e
      # sys.exit(1)
   time.sleep(1.0)
sr. member
Activity: 406
Merit: 250
September 19, 2013, 07:53:09 PM
#17
Nah r3wt that's not how I am. Tongue

Nice that at least we've come to an agreement.

Indeed, let's see what he says.
hero member
Activity: 686
Merit: 504
always the student, never the master.
September 19, 2013, 07:47:59 PM
#16
Anything with an FPGA is never a "basic design", FPGA's are always complicated. There exists no FPGA hardware that costs only $1 per unit. (FPGA is an expensive technology, which is why it is not suitable for any low-cost market segment, like consumer hardware.) You show little literacy about hardware development and failed to answer a technical question that would not release any vital information about the supposedly privately commissioned product.

Honestly I think you sound a lot like a scammer. Videos don't provide any real proof as they can easily be faked and your grammar and word usage sounds like you are 14 years old.

What do you say?

are you stupid? he's talking dollar khash ratio. he wasn't talking about a 1 dollar, complete unit. get off of your horse.

I find it highly suspicious that someone with such a terrible trust rating is defending this guy. :/
its funny you should mention it as well. if  you watched the video it becomes obvious in about 15 fucking seconds that this is real

How can you know that test_miner.py isn't just a script full of echo commands with a time.sleep in between? Or hell, even a CPU miner, which is more or less correct as to what the speed you'd get would be.

Just look at the text output when the script was given a ^C.



Suspicious.

Post the source to test_miner.py, since all it is is a mining client and would not release any confidential information. If it shows legitimate USB or serial port interfacing code of some sort then I'll believe you.
ah okay, then your suspicions are meritorious, i just saw your vague posts and assumed you were trolling or slinging fud towards the OP. i'll hang up and listen for his rebuttal and hope he shares the source.
sr. member
Activity: 406
Merit: 250
September 19, 2013, 07:35:13 PM
#15
Anything with an FPGA is never a "basic design", FPGA's are always complicated. There exists no FPGA hardware that costs only $1 per unit. (FPGA is an expensive technology, which is why it is not suitable for any low-cost market segment, like consumer hardware.) You show little literacy about hardware development and failed to answer a technical question that would not release any vital information about the supposedly privately commissioned product.

Honestly I think you sound a lot like a scammer. Videos don't provide any real proof as they can easily be faked and your grammar and word usage sounds like you are 14 years old.

What do you say?

are you stupid? he's talking dollar khash ratio. he wasn't talking about a 1 dollar, complete unit. get off of your horse.

I find it highly suspicious that someone with such a terrible trust rating is defending this guy. :/
its funny you should mention it as well. if  you watched the video it becomes obvious in about 15 fucking seconds that this is real

How can you know that test_miner.py isn't just a script full of echo commands with a time.sleep in between? Or hell, even a CPU miner, which is more or less correct as to what the speed you'd get would be.

Just look at the text output when the script was given a ^C.



Suspicious.

Post the source to test_miner.py, since all it is is a mining client and would not release any confidential information. If it shows legitimate USB or serial port interfacing code of some sort then I'll believe you.
sr. member
Activity: 308
Merit: 250
September 19, 2013, 07:27:59 PM
#14
Mate..just do your job and hit the market hard  Cheesy ...envy Wink
sr. member
Activity: 406
Merit: 250
LTC
September 19, 2013, 07:20:21 PM
#13
Basic design means this is iteration 59 sub iteration 7 from major iterations 119, just a post for my old thread, some objective answer. I did expect some stir, but I didn't expect so much or I would have post it long ago, lol..
hero member
Activity: 686
Merit: 504
always the student, never the master.
September 19, 2013, 07:19:38 PM
#12
Anything with an FPGA is never a "basic design", FPGA's are always complicated. There exists no FPGA hardware that costs only $1 per unit. (FPGA is an expensive technology, which is why it is not suitable for any low-cost market segment, like consumer hardware.) You show little literacy about hardware development and failed to answer a technical question that would not release any vital information about the supposedly privately commissioned product.

Honestly I think you sound a lot like a scammer. Videos don't provide any real proof as they can easily be faked and your grammar and word usage sounds like you are 14 years old.

What do you say?

are you stupid? he's talking dollar khash ratio. he wasn't talking about a 1 dollar, complete unit. get off of your horse.

I find it highly suspicious that someone with such a terrible trust rating is defending this guy. :/
its funny you should mention it as well. if  you watched the video it becomes obvious in about 15 fucking seconds that this is real
sr. member
Activity: 406
Merit: 250
September 19, 2013, 07:18:35 PM
#11
Anything with an FPGA is never a "basic design", FPGA's are always complicated. There exists no FPGA hardware that costs only $1 per unit. (FPGA is an expensive technology, which is why it is not suitable for any low-cost market segment, like consumer hardware.) You show little literacy about hardware development and failed to answer a technical question that would not release any vital information about the supposedly privately commissioned product.

Honestly I think you sound a lot like a scammer. Videos don't provide any real proof as they can easily be faked and your grammar and word usage sounds like you are 14 years old.

What do you say?

are you stupid? he's talking dollar khash ratio. he wasn't talking about a 1 dollar, complete unit. get off of your horse.

I find it highly suspicious that someone with such a terrible trust rating is defending this guy. :/
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