Topic: FPGA mining for fun and profit - page 12. (Read 67204 times)
Give us the averaged Mhash/power consumption stats for all 16 Xilinx, including the price for one of them, then we can talk.
So I discovered Bitcoin today and soon after that dove into my usual obsessive research mode about mining. The difficulty of generating bitcoins is going to keep going up and the amount of power the current mining rigs I've seen is going to go up. I'm a computer engineer by trade so I'm kind of a bastard of electrical engineering and computer science. I do know FPGAs though. I've got a PICO EX-300 board in my workstation with 16 Xilinx Spartan FPGAs on it. I still have a lot of work to do with optimization of the chips but I've got a single core running at about 117MH/s with a fairly quick and crude design.
I've been using the board to crack WPA 2 at some pretty amazing speeds. If I can put enough time in it I should have a core design that could be loaded on USB/PCIE FPGA boards that'll use a lot less power and have some serious hashing power.
I've been using the board to crack WPA 2 at some pretty amazing speeds. If I can put enough time in it I should have a core design that could be loaded on USB/PCIE FPGA boards that'll use a lot less power and have some serious hashing power.
Looking forward to seeing the final results.
So I discovered Bitcoin today and soon after that dove into my usual obsessive research mode about mining. The difficulty of generating bitcoins is going to keep going up and the amount of power the current mining rigs I've seen is going to go up. I'm a computer engineer by trade so I'm kind of a bastard of electrical engineering and computer science. I do know FPGAs though. I've got a PICO EX-300 board in my workstation with 16 Xilinx Spartan FPGAs on it. I still have a lot of work to do with optimization of the chips but I've got a single core running at about 117MH/s with a fairly quick and crude design.
I've been using the board to crack WPA 2 at some pretty amazing speeds. If I can put enough time in it I should have a core design that could be loaded on USB/PCIE FPGA boards that'll use a lot less power and have some serious hashing power.
I've been using the board to crack WPA 2 at some pretty amazing speeds. If I can put enough time in it I should have a core design that could be loaded on USB/PCIE FPGA boards that'll use a lot less power and have some serious hashing power.
Jump to: