Also, looks like I might be done with the BM1384 two-chip breakout board. I'll hopefully have time to verify it tomorrow and we can send off for some prototype PCBs.
We have a 3.3V UART input (so it can tie off a CP2102 USB-UART adapter like Novak cooked up for Prismas) with an integrated 1.8V level shifter for UART comms to the chips. The two chips on the board can be jumpered for series or parallel operation, and each node has a separate VDD and GND so you can externally power them on a common rail for parallel operation, or tie Node 1 GND to Node 0 VCORE and put a twice-voltage regulator across Node 1 VDD and Node 0 GND for string operation. Multiple boards can be tied in parallel or in series to test different matrix dimensions.
I could test a two-chip string with this board, which once I design the regulator would basically be a breadboard version of Phil's 2-chip USB stick. I'd go for a two-chip string instead of a parallel node because the higher voltage regulator at the same current output will be more efficient, and also because I can probably use the same parts as on the single-chip version.
The silkscreen is loaded with notes for proper use, just in case. If it works as expected I'll be quite pleased.
kilo17 - have you looked at an SP20 board and compared it to an S5 board? The S5 board has zero regulation, just some node-level current buffering capacitors. It has some passive comm level-shifting components. And it uses a standard protocol so no converters are necessary to talk directly to literally any controller ever. Each SP20 board has FOUR four-phase buck converters on it, the parts count for each of which approaches the total count for our entire board. And their protocol is non-standard so it'd have to be bit-banged by software, the timings for which would probably be implementation-dependent.
For another example, compare a Habanero board to an S3. The stock hashrate is about the same, but where the S3 has eight simple 53355DQP regulators, the Habanero has FOUR six-phase digital VRMs. Nothing against the Hab; if it were a woman I'd stick it in 'er, but the level of complexity required to support a large single low-voltage-high-current ASIC is about half an order of magnitude higher than a standard many-small-chips-in-parallel design and a full order higher than a well-thought-out string/matrix of small chips.