Topic: How to make an asic miner from scratch using 16nm Finfet chips from TSMC? (Read 4589 times)

Step one - Write a check for $2-5 million for development.    If you are not prepared for this step, then the rest will not matter.  It is a very expensive endeavour. 

Do not complicate an already complicated task.  Any board and ASIC can be used in immersion cooling.  Obviously there are "better" ways of having the board for fitment issues and if you want the best cooling then a larger surface area on the ASIC would help but those things are nominal.

I would say you have your hands full with just the ASIC design and fab, not to mention that the board design and manufacturing is equally complex.  The best way to get into immersion cooling is to design the cooler around the board design which would obviously come after the ASIC.

heh heh. Long enough to see that yes, everything old is New again. First vacuum tubes - high impedance & voltage controlled, then transistors using low impedance/voltage/higher current and now with all the various members of the FET family back to voltage vs current, Analog > digital and now > mixed level digital (more functional states per-gate but with higher power needs as well) which to me is headed back to quasi analog computers....

I'll check out the thread.

I'll also add that ja the ASIC's are key to what can be processed but as the poster child of failed board design and manufacturing shows (Bitmine.ch), all the support circuitry and attention to board layout/physical construction is just as critical to pay attention to

Dude, you've been an engineer longer than I've been alive.

I don't know how useful my BM1384 dev thread would be, but there was some good discussion in there somewhere when PlanetCrypto was talking about running out his own chip.

  Why thank ye for the plug . Coming from you I take that as rather high praise
Since we are in disclaimer mode here: I too have never laid out silicon. I do not know or care to know the actual hardwired logic pathways in mining ASIC's. I do know more than a thing or 2 about high speed circuitry and the care/feeding thereof... My first experience with high-speed circuit layout originally comes from working with/building microwave coms gear in the early 1970's. Thing is, with the logic switching speeds ASIC's use all the same rules apply regarding local power decoupling and signal integrity vs the path routing. It is not only clock speed that gets you. More problematic is the rise/fall times of the signals inducing high levels of very localized odd-harmonics into the power plane and data signals.

Anywho, for the past 39 years my biz has been designing/building from framework to the control boards equipment used in some rather critical steps in chip fab processes. We build bleeding edge tech that makes making bleeding edge chips possible. That in turn is where my contacts with the semiconductor bix comes from. Natural curiosity and the need to know about all steps and I mean all involved is what keeps me current on what node-sizes the various major foundries can produce;) As for my blasting pre-packaged IP blocks a foundry or chip design house can provide, it is a common sense  item any decent chip designer should follow if the goal is Best-in-Class. Far more risky yes because simulate all you want, until it is physically produced there is no third-party assurance (someone else to blame) that each function block actually does what it should.

If you want a 'safe' moderate performance  first run chip as proof of concept, then use pre-packaged IP function blocks. They are proven to work and just need to be placed best as possible in the die and linked together anyway ya can. *That* is along the line of what that chip design site mentioned earlier on sounds like they do. At the more mature 22nm and higher nodes foundries can often provide short-runs by using 'spare' space on wafers to make more money per-wafer on what is often razor-thin margins from generic chips made on the same wafers. I rather doubt that 'low cost' option is yet available at 16/14nm. Scrap rate is still too high

As for hashing ASIC's themselves I highly recommend reading through the A1 chip dev thread starting here. https://bitcointalk.org/index.php?topic=294235.360. I dived in there due to my ordering on of the ill-fated AMT/Bitmine.ch A1 based miners in Feb. 2014. It is a good read on the trial and tribulations of giving birth to a new miner design. Also points to, hell, screams where Bitmine.ch went so very wrong with their boards...

Enough of the mutual admiration club and back to the Topic. To the OP I say, if you think you have a core team that can do it then go for it. The mining community needs hardware choices. Just fully research what is going to be involved and round up (fully informed of the risks) investors. Again, I highly recommend that A1 dev thread for insite on what to expect.

Well, I'd fall back to 2112 and the rest for any kind of chip-level stuff. I haven't worked with logic in a while, and really never with even FPGA innards design. There's probably a lot of folks around who are better board engineers too, like NotFuzzyWarm and some others.

Novak and I are working toward an immersion cooled board, but that's kind of a contract job. We don't particularly like high density or exotic cooling requirements.

Can you post a couple of his designs here?

P.s. - I wanna go with emersion cooling. So, if anyone has a good layout for it, it'd be great.

And you should listen to this guy, he has actually product-engineered a system using a proprietary chip. Despite his modesty that's just as hard a task as designing the silicon!

Thank you for your opinion sir, I really admire what you've said. On th other hand thank you again for boosting my confidence level to do so.

I fully admit to having zero silicon-level design experience, just a bit of miner design using someone else's chips. No advice on chip design here, except maybe opinions on packaging and features that could make the board-level and controls stuff easier.

Firstly, let me say that I very much admire your goal of wanting to make a new chip, I sincerely hope you are successful.

The main obstacle to you succeeding is finance - to build a 16nm chip will mean an NRE of around $5 - 7 Million dollars, depending on which route you choose, and that's a huge amount of money to get hold of. Having said that, a complete bunch of chancers called KNC raised a lot more than that for their first offering, so you never know. You've also got the cost of renting design tools and all the expenses that go with running a company. You might be able to get a slot on a 16nm MPW run, but you'll still be looking at over $1m if you want to have any chance of getting a prototype.

The best advice I can give you is to ignore most of what you read on this forum, it's full of 'experts' (who are anything but) who are only interested in given their opinion on all things silicon design wise. Needless to say, virtually none of them have actually designed  anything electronic of any complexity let alone a chip, so be careful what advice you take. The real experts, and there are a handful, will give you useful and practical advice rather then repeat what they've read on Wikipedia.

If your design guy is any good he will quickly figure out how simple SHA256 is, it's really just full adders and flip flops with some very simple logic thrown in and if he looks to academic articles he'll get a lot more ideas than he'll ever find on this forum.

Good luck!

Okay! so, does anyone here has a design layout? and is anyone interested to work on it with me?


P.s. - Anyone and everyone are welcome

I guess practice makes perfect

Any correlation to them changing to using string topology vs multiple buck regulators with chips fed from a common power plane (in banks)? I sorta wonder how much interaction with the buck switching freq vs core freq they were seeing...

If I'm thinking right, the BM1380 had 8 cores, BM1382 had 63, BM1384 at 55 and BM1385 at 50. At least that's how the frequency-hashrate scaling worked out. So they've actually been shrinking for the last two generations.

Query: are Bitmains chips uni-planar or a 3d stack like the A1's were? In an ultimate case of using pre-packaged IP InnoSilicon as I recall had the cores, then a memory layer topped by an SPI coms layer. Each separate silicon tied together with ISV's and wire bonds.

^^ +1 !
Throw in the fact that design rules for 16/14nm nodes is still a Work-in-Progress because the mfg processes are as well and you see why after years of promises those nodes are just now becoming available to companies other than IBM, Intel, AMD, and Samsung et al.

Maybe somebody at Bitmaintech read the documentation to their synthesis tool all the way to the end (and with understanding   ?)

The problem with SHA-256 is that it causes very slow convergence in the automatic synthesis tools. Because there are no external timing constraints (see https://en.wikipedia.org/wiki/Timing_closure ) the optimization algorithm has no real direction to seek and starts very slowly searching the humongous design space of filling out the chip with hashing engines. Adding some artificial constraints greatly improves the speed of convergence by avoiding unnecessarily spending time on obviously unproductive (to a human) design variants.

For example see my avatar: it is a floorplan of completely unrestrained implementation of a single fully unrolled SHA256D pipeline. The synthesis algorithm self-placed both input and output pins to the I/O bank at the center of the chip and then routed around that bank. Yellow is the first SHA-256, green is the second SHA-256.

Compare it with a hand-restrained design by eldentyrell where he intelligently squeezed 1.5 times more hashing into a smaller chip: https://bitcointalksearch.org/topic/algorithmically-placed-fpga-miner-255mhschip-supports-all-known-boards-49971

thanks for the correction om chip #'s  was an off the top of me head dismembering of them

As for the freq/core voltage, probably has to do with how well the data eye can be kept open over the chips internal signal paths between the different parts (coms, memory, cores). That bit is where custom routing helps immensely because you can layout the I/O of each block to provide the shortest paths to the other function blocks. Shorter path = lower capacitance to charge/discharge = faster speeds at same or hopefully also lower power consumption.

Dinna know that Bitmain gained enough to actually use fewer cores per chip and still get the results they got.

Not entirely the same, as BM1385 has 50-core versus BM1384's 55 cores. I'm not sure how operating frequency versus voltage changes at the same node size, but BM1385 runs about 600MHz at 670mV where BM1384 was comfortable at about 225MHz at that voltage. Course, some 28nm procesor designs have easily broken 1GHz. What would make that difference?

Well sounds like a good start. The chip designer is a person who will be critical as I suspect that design site will be pushing you to use pre-packaged IP function blocks that are just linked together to create the desired chip functions. While that can work using pre-packaged IP also means that you will be making the signal connection paths based on what the IP block gives you - that in turn means non-optimal performance. Prime example of the difference custom routing gives you is Bitmains '1384 vs their '1385 chips. Same circuitry but by using custom routing in the '1385 function blocks themselves Bitmain drastically improved the power/hashing performance.